Solve the video noise problem of DM8168 CameraLink, dm8168cameralink

Solve the video noise problem of DM8168 CameraLink, dm8168cameralink

A few days ago, I wrote an FPGA-based LVDS video (Noise Removal). At that time, the CameraLink video encountered a lot of noise, which was unsightly and had no hardware problems, the FPGA at the front-end of the collection can only be re-processed using the hardware description language, and the effect has been improved. In fact, you are deceiving yourself and having hardware defects, when the video data source is not accurate, it is impossible to achieve perfect results. At that time, four possibilities were analyzed:

① DS90CR288 solve the problem of insufficient power supply for the serial chip.
② The differential line impedance does not match the 100 euro resistance (the transmission line is short and less likely ).
③ The video line is not synchronized (the video line is not likely to be processed after a long wait)
④ The TOP layer adopts the video data line and clock line. Does the TTL signal cause crosstalk to the current on the differential line? Is TTL far from the matching resistor?
Finally, Practice has proved that none of them is correct... My DM8168 board has two video input interfaces: CameraLink input and YPbPr video input. The main core devices are Cyclone IV and TI's TVP7002. To save the wiring strength, I connected the two video data cables to the VIN0 port of DM8168, that is, the video cable was split into forks. To ensure the purity of a single video data, we must completely avoid the impact of another chip pin on the video line. When the board is made, the power supply of TVP7002 and the power supply of Cyclone IV are configured with a dial switch to control power supply disconnection. When testing the YPbPr video input, the Cyclone IV power supply is disconnected to collect videos that show high-definition noise. Then, when the CamLink video is tested, the power supply on the 7002 power supply pin is disconnected (PIN26, 41, 53, 66) and the video noise is detected, therefore, FPGA is used to collect LVDS videos (Noise Removal ). I tested the voltage parameters in various places today and found that the TVP7002 pin (PIN26, 41, 53, 66) that was supposed to be suspended was not purely suspended, therefore, all the power supplies related to TVP7002 (except the four 3.3V Power Supply pins) are forcibly grounded, and the system is powered on and started to run the collection display program. The previous problems are eliminated, happy. I did not think about it for weeks, causing negative consequences. Fortunately, I swallowed it up. Otherwise, I am sorry for my mentor, and I wasted his money on graduation.