文章目錄
- Verilog HDL Coding Style Proposal
Verilog HDL Coding Style Proposal一、寫在前面的話
話說Bingo觸摸FPGA也有幾年了,一開始學的VHDL,後來跟上了時代的潮流,又自學了Verilog,一直保持到了今天,似乎早已淡忘了VHDL的身影。
一開始的模仿,接下來不懂就查,直到最後掌握基本的代碼規範,到此刻為止,從來沒有看過altera官方的Verilog Coding Style。終於,此刻,下定決心,來規範一下自己的代碼。
好的代碼不僅是寫給自己看的,更是為了讓別人欣賞。一段完美代碼,每一個毛孔都是那麼的無懈可擊。嚴格的規範,唯美的風格,賞心悅目,窺一斑可見整體。作為一個優秀的工程師,不管是軟體工程是還是硬體工程師,養成良好的代碼規範,於己於人,都將會有事半功倍的好處,因此,“唯美”,從此刻開始!
Altera_Verilog_Coding_Style.pdf
:
1) www.altera.com
2) www.chinaaet.com
二、規範我們的代碼1. 命名規範
我謹代表altera_verilog_coding_style.pdf,摘要了一些一般人不太注意甚至不知道的規則,希望那些不明真相的群眾,能夠從此看到自己的靈魂。
1) Use uppercase letters for all parameter names
2) Clock name should be clk or prefixed with clk
3) Active high reset signal should be prefixed with rst; Active low reset should be named rst_n
4) Three state signal name should have suffix _z
5) Instance names should begin with ‘U_’
6) Use a separate line for each HDL statement
7) Use four space code indentation
8) Operand sizes should match
2. 推介檔案頭格式
對於一段稱得上“唯美”的代碼,切不可少了龍頭。所謂檔案頭,很多人不曾注意,這不僅僅是在於表面的注釋自己,更重要的是能夠養成規範的團隊代碼規範,讓第三方能夠更好的認知,修改,移植。
/*-------------------------------------------------------------------------
This confidential and proprietary software may be only used as authorized
by a licensing agreement from CrazyBingo.
(C) COPYRIGHT 2012 CrazyBingo. ALL RIGHTS RESERVED
Filename : led_matrix_display.v
Author : CrazyBingo
Data : 2012-01-18
Version : 0.1
Description : This file has the module of led_matrix_display top.
Modification History :
Data By Version Change Description
===========================================================================
12/01/18 CrazyBingo 0.1 Original
--------------------------------------------------------------------------*/
3. 時鐘設計規則
很多時候,一個稍大的工程,一段自以為完美的代碼,往往死在時鐘之上,或是同步非同步時鐘,或是門控使能時鐘,多半不明真相的群眾,還是不能夠掌握Verilog的時鐘設計規則。
1) Buffers should not be explicitly added to clock path
2) Gated clocks are not allowed in the design(just use enable clock)
3) Clock should be visible from top unit. We recommend that designer can use block PLL/DLL to generate the internal clocks which can be distinguished by compile tool better
4) Use synchronous methodology to cross clock domain
5) Use synchronous methodology to cross clock domain
Asynchronous reset,synchronous release 非同步複位,同步釋放
6) Avoid internally generated reset/set/load
7) There should be at most one synchronous reset/set/load signal in a sequential block
4. 可綜合之設計
1) Use 'if(<%context> == 'b1)' for rising edge asynchronous reset/set/load expressions
2) Use 'if(<%context> == 'b0)' for falling edge asynchronous reset/set/load expressions
3) Do not use initial constructs to initialize signals
4) Avoid inferring latches in design(case,if...else...)
5) Code state machines description with two or there blocks
6) Use parameter statements to define the state vector of a state machine(推介三段式)
5. 基本劃分規則
1) Locate related combinational logic in a single module
2) Separate Modules That Have Different Design Goals
3) Partition asynchronous logic from synchronous logic
4) Arithmetic operators: Merging resources
5) Eliminate glue logic at the top level(粘合邏輯:兩個例化模組中間的logic)
6) If equation is needed to evaluate clock enable, use separate statement