Configuring the GPIO pins on the Linux kernel layer and the user layer

The basis for Linux BSP development is to deal with Gpio, which summarizes the knowledge of the Gpio control of a development board over the next few days.

The company's development Board is DTB mode, first, enter the Dts,dtsi file to view the module about Gpio.

Soc {.                .        . Gpio0: [Email protected]****Addr {compatible="**********"; Reg= <00x****addr0 0x50>; Interrupts= <spi4Irq_type_level_high>; #gpio-cells = <2>; Gpio-Controller; Gpio-ranges = &LT;&AMP;PFC0 0  ->; #interrupt-cells = <2>; Interrupt-Controller; Clocks= <&cpg Cpg_mod912>; Power-domains = <*****>;               };               .               . .};

You can see that the Gpio node hangs on the SOC node, and the Development Board in hand divides the Gpio into 8 Bank:gpio0-gpio7

Reg =<0 Address 0 length >

#gpio-cells =<2> indicates that a gpio pin is to be described with 2 cells

As defined in I²c: Pwd-gpios = <&gpio6 7 gpio_active_high>;

The GPIO that represents bank 6 is described by 2 cells: 7,gpio_active_high (7 indicates that the seventh pin under Bank 6 is typically GP 6_07; Gpio_active_high is active on the high level)

Gpio-controller; Interrupt-controller; Indicates that the pin at bank 0 can be either an interrupt pin or a generic GPIO pin

Gpio-ranges = <&PFC 0 0 16>; Indicates 16 gpio pins at Bank 0

GPIO is driven using Pinctrl mode, PIN control subsystem:

1. Enumerate all available pin pins, so that each pin has a unique ID (num), which is critical for future operations.

　　　　

enum {    0,    pinmux_data_begin,    /*  add  gp_0_1_data*/      pinmux_data_end,#define f_ (x, y) ...}

2. Manage these pin pins, as the pin can be reused such as SPI and GPIO multiplexing a pin pin such as: Gp2_08/miso, thus extending the PIN group and pin Functon two concepts:

    i2c2_pins:i2c2 {        "i2c2_a";         " I2C2 " ;    };

In DTS, as shown above, where i2c2_a is shown in the Pinctl source code, the two pins of i²c use Gp5_0, Gp5_4.

Static Const int i2c2_a_pins[] = {    /**    /Gp_pin (5  0), Gp_pin (54),};

The function is as follows:

struct sh_pfc_function {    constChar *name;     Const Char Const *groups;     int nr_groups;}; #define Sh_pfc_function (n = i2c2)                \    {                                = #n,                        = n# #_groups,                    =  Array_size (n# #_groups),        }

Well, the basic idea is to write so much first.

Kernel Layer Configuration GPIO

If you want to configure a GPIO pin while writing the kernel driver, you can add it in DTS: Pwd-gpios = <&gpio0 7 gpio_active_high>;

In the driver code, you need to include #include <linux/gpio.h> use:

gpio_id = Of_get_named_gpio (Your_driver->dev->of_node, "Pwd-gpios", 0);

Obtain the ID number of the gp0_07, and then request a Gpio action object.

if (Gpio_is_valid (gpio_id))//Determine if an IO is legal

Devm_gpio_request_one (&platform_device->dev, Gpio_id,gpiof_out_init_low, name);

Set the direction of the Gpio if the output is set at the same level:
/* Set as input or output, returning 0 or negative errno */
int gpio_direction_input (unsigned gpio);
int gpio_direction_output (unsigned gpio, int value);

To get the level of the input pin:
/* GPIO Input:return zero or nonzero */
int Gpio_get_value (unsigned gpio);

Set Output:
void Gpio_set_value (unsigned gpio, int value);

Release the requested Gpio object

void Gpio_free (unsigned gpio);

To map a gpio to an IRQ interrupt:
/* Map GPIO numbers to IRQ numbers */
int Gpio_to_irq (unsigned gpio);

/* Map IRQ numbers to GPIO numbers (avoid using this) */
int Irq_to_gpio (unsigned IRQ);

To set the Gpio IRQ interrupt type:

Set_irq_type (GPIO_TO_IRQ (Gpio), irq_type_edge_falling);

User Layer Configuration GPIO

You need to confirm the Device Drivers-"GPIO support set y in the kernel menuconfig.

In the/sys/class/gpio directory, the following is shown below:

[Email protected]:/sys/class/gpio# lsexport         gpiochip361  gpiochip419  gpiochip453  gpiochip496gpiochip357  gpiochip393  gpiochip437  gpiochip468  unexport

The number behind the gpiochip is the base address of each bank, which is GP0 correspondence gpiochip468

So the ID of gp0_07 is 468 + 7; (maybe different kernel versions, or the development Board is not the same) by:

[Email protected]:/sys/class475 > Export

The gpio475 directory is generated for the corresponding

[Email protected]:/sys/class/gpio/gpio475# lsactive_low  device  direction  Edge  Power  subsystem  uevent  value

Pass

[Email protected]:/sys/class1 >value [email protected]-x:/sys/class0 >value[email protected]-x:/sys/class"in" > Direction [Email protected] -x:/sys/class"out"

To control the output input, level high and low.

Finally, there is too much to write about Pinctrl, just write it first ...

Too late to write reference documents, the specific combination of Wowotech and the company's equipment, to work ...

Configuring the GPIO pins on the Linux kernel layer and the user layer