Digital Integrated Circuit Design-13-common modules

Digital Integrated Circuit Design-13-common modules
Introduction

C language, C ++ language and other software programming languages attract us a very important reason is that they can provide a very rich library for us to use, greatly improving the coding efficiency.

However, this aspect of the HDL language, such as verilogHDL, is relatively weak, especially the Comprehensive syntax. there is basically no general module library for us to use, so the coding efficiency will be relatively low. If we accumulate some frequently used modules and gradually standardize them, it will be much easier for us to design new circuits. Today is the beginning.

1. Determine whether two signals are equal

function Fcompare;input valid_a,valid_b;input [31:0] a,b;Fcompare = valid_a & valid_b & (({32{valid_a}} & a) == ({32{valid_b}} & b));endfunction

2. For a one-hot value, the corresponding bit decimal number is obtained.

function [2:0] Fcode_8b;input [7:0] one_hot;Fcode_8b =( one_hot[0] ? 3'd0 :one_hot[1] ? 3'd1 :one_hot[2] ? 3'd2 :one_hot[3] ? 3'd3 :one_hot[4] ? 3'd4 :one_hot[5] ? 3'd5 :one_hot[6] ? 3'd6 :one_hot[7] ? 3'd7 : 3'd0;);endfunction

3. Reverse functions of the above function

function [7:0] Fdecode_8b;input [2:0] value;Fdecode_8b =( value==3'd7,value==3'd6,value==3'd5,value==3'd4,value==3'd3,value==3'd2,value==3'd1,value==3'd0 );endfunction

4. clock gage

In actual circuit design, low-power is a rule we must keep in mind at all times. The most important thing in the implementation of this rule is clock gage.

However, DC usually provides a dedicated gating cell. During simulation, we still need a simple model.

module clk_gate(input enable,input clk,output clk_o);reg not_gate;always @(enable or clk)if(~clk)not_gate = enable;assign clk_o = clk & not_gate;endmodule

5. Obtain the rising edge of the signal.

module sig_posedge(input clk,input signal,output signal_posedge);reg tmp_r;always @(posedge clk)tmp_r <= signal;assign signal_posedge = signal & ~tmp_r;endmodule

6. Obtain the descent edge of the signal.

module sig_negedge(input clk,input signal,output signal_negedge);reg tmp_r;always @(posedge clk)tmp_r <= signal;assign signal_negedge = ~signal & tmp_r;endmodule

7, round-robin arbiter (2 to 1)

function [1:0] Fround_robin_2;input [1:0] req,req_en,grant_en;input priority_in;reg rq_a,rq_b,grant_a,grant_b,prio_a,prio_b;begin{rq_a,rq_b} = req;{prio_b,prio_a} = {priority_in==1'b1,priority_in==1'b0};grant_a = ( prio_a & rq_a |prio_b & rq_a & ~rq_b);grant_b = ( prio_b & rq_b |prio_a & rq_b & ~rq_a);Fround_robin_2 = {grant_b,grant_a} & req_en & grant_en;endendfunction

8, round-robin arbiter (4 to 1)

function [3:0] Fround_robin_4;input [3:0] req,req_en,grant_en;input [1:0] priority_in;reg rq_a,rq_b,rq_c,rq_d;reg grant_a,grant_b,grant_c,grant_d;reg prio_a,prio_b,prio_c,prio_d;begin{rq_d,rq_c,rq_b,rq_a} = req;{prio_d,prio_c,prio_b,prio_a} = {priority_in==2'b11,priority_in==2'b10,priority_in==2'b01,priority_in==2'b00};grant_a = ( prio_a & rq_a |prio_b & rq_a & ~rq_b & ~rq_c & ~rq_d |prio_c & rq_a & ~rq_c & ~rq_d |prio_d & rq_a & ~rq_d);grant_b = ( prio_b & rq_b |prio_c & rq_b & ~rq_c & ~rq_d & ~rq_a |prio_d & rq_b & ~rq_d & ~rq_a |prio_a & rq_b & ~rq_a);grant_c = ( prio_c & rq_c |prio_d & rq_c & ~rq_d & ~rq_a & ~rq_b |prio_a & rq_c & ~rq_a & ~rq_b |prio_b & rq_c & ~rq_b);grant_d = ( prio_d & rq_d |prio_a & rq_d & ~rq_a & ~rq_b & ~rq_c |prio_b & rq_d & ~rq_b & ~rq_c |prio_c & rq_d & ~rq_c);Fround_robin_4 = {grant_d,grant_c,grant_b,grant_a} & req_en & grant_en;endendfunction

9, round-robin arbiter (8 to 1)

function [7:0] Fround_robin_8;input [7:0] req,req_en,grant_en;input [2:0] priority_in;reg rq_a,rq_b,rq_c,rq_d,rq_e,rq_f,rq_g,rq_h;reg grant_a,grant_b,grant_c,grant_d,grant_e,grant_f,grant_g,grant_h;reg prio_a,prio_b,prio_c,prio_d,prio_e,prio_f,prio_g,prio_h;begin{rq_h,rq_g,rq_f,rq_e,rq_d,rq_c,rq_b,rq_a} = req;{prio_h,prio_g,prio_f,prio_e,prio_d,prio_c,prio_b,prio_a} = {priority_in==3'b111,priority_in==3'b110,priority_in==3'b101,priority_in==3'b100,priority_in==3'b011,priority_in==3'b010,priority_in==3'b001,priority_in==3'b000};grant_a = ( rq_a &(prio_a|prio_b & ~rq_b & ~rq_c & ~rq_d & ~rq_e & ~rq_f & ~rq_g & ~rq_h|prio_c & ~rq_c & ~rq_d & ~rq_e & ~rq_f & ~rq_g & ~rq_h|prio_d & ~rq_d & ~rq_e & ~rq_f & ~rq_g & ~rq_h|prio_e & ~rq_e & ~rq_f & ~rq_g & ~rq_h|prio_f & ~rq_f & ~rq_g & ~rq_h|prio_g & ~rq_g & ~rq_h|prio_h & ~rq_h);grant_b = ( rq_b &(prio_b|prio_c & ~rq_c & ~rq_d & ~rq_e & ~rq_f & ~rq_g & ~rq_h & ~rq_a|prio_d & ~rq_d & ~rq_e & ~rq_f & ~rq_g & ~rq_h & ~rq_a|prio_e & ~rq_e & ~rq_f & ~rq_g & ~rq_h & ~rq_a|prio_f & ~rq_f & ~rq_g & ~rq_h & ~rq_a|prio_g & ~rq_g & ~rq_h & ~rq_a|prio_h & ~rq_h & ~rq_a|prio_a & ~rq_a);grant_c = ( rq_c &(prio_c|prio_d & ~rq_d & ~rq_e & ~rq_f & ~rq_g & ~rq_h & ~rq_a & ~rq_b|prio_e & ~rq_e & ~rq_f & ~rq_g & ~rq_h & ~rq_a & ~rq_b|prio_f & ~rq_f & ~rq_g & ~rq_h & ~rq_a & ~rq_b|prio_g & ~rq_g & ~rq_h & ~rq_a & ~rq_b|prio_h & ~rq_h & ~rq_a & ~rq_b|prio_a & ~rq_a & ~rq_b|prio_b & ~rq_b);grant_d = ( rq_d &(prio_d|prio_e & ~rq_e & ~rq_f & ~rq_g & ~rq_h & ~rq_a & ~rq_b & ~rq_c|prio_f & ~rq_f & ~rq_g & ~rq_h & ~rq_a & ~rq_b & ~rq_c|prio_g & ~rq_g & ~rq_h & ~rq_a & ~rq_b & ~rq_c|prio_h & ~rq_h & ~rq_a & ~rq_b & ~rq_c|prio_a & ~rq_a & ~rq_b & ~rq_c|prio_b & ~rq_b & ~rq_c|prio_c & ~rq_c);grant_e = ( rq_e &(prio_e|prio_f & ~rq_f & ~rq_g & ~rq_h & ~rq_a & ~rq_b & ~rq_c & ~rq_d|prio_g & ~rq_g & ~rq_h & ~rq_a & ~rq_b & ~rq_c & ~rq_d|prio_h & ~rq_h & ~rq_a & ~rq_b & ~rq_c & ~rq_d|prio_a & ~rq_a & ~rq_b & ~rq_c & ~rq_d|prio_b & ~rq_b & ~rq_c & ~rq_d|prio_c & ~rq_c & ~rq_d|prio_d & ~rq_d);grant_f = ( rq_f &(prio_f|prio_g & ~rq_g & ~rq_h & ~rq_a & ~rq_b & ~rq_c & ~rq_d & ~rq_e|prio_h & ~rq_h & ~rq_a & ~rq_b & ~rq_c & ~rq_d & ~rq_e|prio_a & ~rq_a & ~rq_b & ~rq_c & ~rq_d & ~rq_e|prio_b & ~rq_b & ~rq_c & ~rq_d & ~rq_e|prio_c & ~rq_c & ~rq_d & ~rq_e|prio_d & ~rq_d & ~rq_e|prio_e & ~rq_e);grant_g = ( rq_g &(prio_g|prio_h & ~rq_h & ~rq_a & ~rq_b & ~rq_c & ~rq_d & ~rq_e & ~rq_f|prio_a & ~rq_a & ~rq_b & ~rq_c & ~rq_d & ~rq_e & ~rq_f|prio_b & ~rq_b & ~rq_c & ~rq_d & ~rq_e & ~rq_f|prio_c & ~rq_c & ~rq_d & ~rq_e & ~rq_f|prio_d & ~rq_d & ~rq_e & ~rq_f|prio_e & ~rq_e & ~rq_f|prio_f & ~rq_f);grant_h = ( rq_h &(prio_h|prio_a & ~rq_a & ~rq_b & ~rq_c & ~rq_d & ~rq_e & ~rq_f & ~rq_g|prio_b & ~rq_b & ~rq_c & ~rq_d & ~rq_e & ~rq_f & ~rq_g|prio_c & ~rq_c & ~rq_d & ~rq_e & ~rq_f & ~rq_g|prio_d & ~rq_d & ~rq_e & ~rq_f & ~rq_g|prio_e & ~rq_e & ~rq_f & ~rq_g|prio_f & ~rq_f & ~rq_g|prio_g & ~rq_g);Fround_robin_8 = {grant_h,grant_g,grant_f,grant_e,grant_d,grant_c,grant_b,grant_a} & req_en & grant_en;endendfunction