Linux Kernel Series-8. Clock interruption of operating system development

External interrupts are complicated because of the need to establish a correspondence between hardware interrupts and vector numbers. External interrupts are divided into non-shielded interrupts (NMI) and masked interrupts, which are received by the CPU's two pin NMI and intr, respectively. As shown in the following:

The relationship between the shielded interrupt and the CPU is established by the programmable interrupt controller 8259A. 8259A can be thought of as a proxy for all peripheral devices in the interrupt mechanism. When the BIOS initializes it, IRQ0~IRQ7 is set to the corresponding vector number 08h~0fh, the vector number 08h~0fh is already occupied in protected mode, so we have to reset the master-slave 8259A.

The 8259A setting is not complicated by writing a specific ICW to the appropriate port. The main 8259A corresponding port address is 20h and 21h, the corresponding port address from 8259A is a0h and a1h. ICW a total of 4. The initialization process is as follows:

1. Write the ICW1 to Port 20h (main slice) or a0h (from the slice).

2. Write the ICW2 to Port 21h (main slice) or a1h (from the slice).

3. Write the ICW3 to Port 21h (main slice) or a1h (from the slice).

4. Write the ICW4 to Port 21h (main slice) or a1h (from the slice).

The order of the 4 steps is not reversed.

The ICW format is as follows

Init8259a:moval, 011hout020h, AL; Lord 8259, Icw1.callio_delayout0a0h, AL; From 8259, Icw1.callio_delaymoval, 020h; IRQ0 corresponding interrupt vector 0x20out021h, AL; Main 8259, Icw2.callio_delaymoval, 028h; IRQ8 corresponding interrupt vector 0x28out0a1h, AL; From 8259, Icw2.callio_delaymoval, 004h; IR2 should be 8259out021h, AL; Main 8259, Icw3.callio_delaymoval, 002h; Corresponds to the main 8259 ir2out0a1h, AL; From 8259, Icw3.callio_delaymoval, 001hout021h, AL; Lord 8259, Icw4.callio_delayout0a1h, AL; From 8259, Icw4.callio_delaymoval, 11111110b; Just turn on the timer interrupt; moval, 11111111b; Shield Master 8259 All interrupts out021h, AL; Main 8259, Ocw1.callio_delaymoval, 11111111b; Shielded from 8259 all interrupts out0a1h, AL; From 8259, Ocw1.callio_delayret

We have shielded all external interrupts by operating on ports 21h and a1h, writing to OCW and using it in the following two scenarios:

1. Block or open an external interrupt.

2. Send EOI to 8259A to notify it to interrupt the processing end.

If you want to block or open an external interrupt, simply write the OCW1 to 8259A. The OCW1 format is as follows:

If you want to block an interrupt, set the corresponding bit to 1. EOI is when each interrupt processing ends, you need to send a EOI to 8259A in order to continue receiving interrupts. The sending EOI is implemented by writing OCW2 to Port 20h or a0h. The format of the OCW2 is as shown.

Send EOI to 8259A can be done by the following code:

mov al, 20hout 20h or a0h, AL

This time we're going to turn on the clock interrupt (IRQ0), the occurrence of an externally masked interrupt is affected by two factors, only if the IF bit is 1, and the corresponding bit of IMR is 0 o'clock.

So, if we want to turn on the clock interrupt, we should not only design an interrupt handler, but also set the IMR, and set the IF bit. Setting IMR can be done by writing OCW2, and setting if can be done by the instruction STi.

Write a clock interrupt handler first

_clockhandler:clockhandlerequ_clockhandler-$ $incbyte [GS: ((80 * 0 + 70) * 2)]; Screen No. 0, column 70th. Moval, 20hout20h, AL; Send eoiiretd

Modify the code that initializes 8259A, the clock interrupt is no longer blocked

Moval, 11111110b; Just turn on the timer interrupt; moval, 11111111b; Shield Master 8259 All interrupts out021h, AL; Main 8259, Ocw1.callio_delaymoval, 11111111b; Shielded from 8259 all interrupts out0a1h, AL; From 8259, Ocw1.callio_delay

To modify IDT:

%rep 32gateselectorcode32, Spurioushandler,      0, Da_386igate%endrep.020h:gateselectorcode32,    ClockHandler,      0, Da_386igate%rep 95gateselectorcode32, Spurioushandler,      0, Da_386igate%endrep.080h:gateselectorcode32,  Userinthandler,      0, Da_386igate

Operation Result:

" Source "

Linux Kernel Series-8. Clock interruption of operating system development