Gic__linux of Linux-arm Interrupt system

These days the outbreak of avian flu in the Yangtze River delta, even the market are afraid to approach, quite a bit of SARS posture, I really doubt God is not a program ape, making people do so many bugs,

H7N9 driver has not written well, the harm we can not stop playing patch, from time to time to a oops. Today, I read an expert's commentary: "The H7N9 gene has eight, the H7 part of which is the wild birds from Zhejiang,

N9 is a part of the wild birds from South Korea, then the remaining six is believed to be from the north of the Yangtze River, "Well, you are South Korea."

1. "Stand the high urine of the far"

GIC for interrupt controllers, do not mix with arm core interrupts, these interrupts are connected to the arm core IRQ or FIQ.

To understand arm interrupt system, GIC is absolutely not to be missed, to first pay a picture of everyone can Baidu to.

+ + and * can be used in safe mode without consideration.

GIC can be used for a single core multi-core system, at which point the simple interruption of the microcontroller is thrown away, from the picture is SGI (software-generated interrupt), PPI (Private peripheral interrupt), SPI (Shared Peripheral interrupt), as the name implies SGI for software can trigger interrupts, often used for communication between the core, PPI for each core of the private peripherals interrupted, SPI for each core public interruption.

Sgi:0~15

Ppi:16-31

spi:32~1019

2. Follow me

The GIC is usually divided into two parts, a Distributor (distributor) and a CPU interface.

The distributor should actually be called a aggregator, and in the back-end design of the IC, layout will mix the interrupt lines from each module to the GIC (the three interrupts mentioned above), and then interrupt the mixed aggregation to the IRQ line on the CPU.

So the core is tactile.

3. Model

Since it is an interrupt controller, it is essential that total interrupts are enabled, each child interrupt enabled, prioritized, and in multi-core systems for SGI to specify which CPU core the interrupt is destined for.

How to ensure that the interruption is not lost. Ah, yes, that's right. Pending,distributor will collect the interruption, first cache, and then to CPU processing, CPU read an interruption, in fact

is to read a register, only this register is the interrupt number, when the state of interruption from pending to ACTIVE,CPU processing, the interrupt number written to the GIC, told

GIC I'm done with it, you can take a break.