Makefile variable assignment, makefile assignment

Makefile variable assignment, makefile assignment

When defining the value of a variable, we can use other variables to construct the value of the variable. There are two methods in Makefile to define the value of the variable.

First, let's look at the first method, that is, simply using the "=" sign, on the left side of "=" is the variable, and on the right side is the value of the variable, the value of the variable on the right can be defined in any part of the file. That is to say, the variable on the right is not necessarily a defined value. It can also use the value defined later. For example:

Foo = $ (bar)
Bar = $ (ugh)
Ugh = Huh?

All:
Echo $ (foo)

When we execute "make all", the value of the variable $ (foo) is "Huh ?" ($ (Foo) is $ (bar), $ (bar) is $ (ugh), and $ (ugh) is "Huh ?") It can be seen that variables can be defined using the following variables.

This function has both good and bad features. The good thing is that we can push the real value of the variable to the end for definition, such:

CFLAGS = $ (include_dirs)-O
Include_dirs =-Ifoo-Ibar

When "CFLAGS" is expanded in the command, it will be "-Ifoo-Ibar-O ". But there is also a bad thing about this form, that is, recursive definition, such:

CFLAGS = $ (CFLAGS)-O

Or:

A = $ (B)
B = $ ()

This will bring make into the infinite variable expansion process. Of course, our make is capable of detecting such a definition and reporting an error. In addition, if a function is used in a variable, this method will slow our make runtime. What's worse, he will use two make functions "wildcard" and "shell" to make unpredictable errors. Because you don't know how many times these two functions will be called. Http://hovertree.com/menu/linux/

To avoid this method, we can use another method in make to define variables. This method uses the ": =" operator, for example:

X: = foo
Y: = $ (x) bar
X: = later

It is equivalent:

Y: = foo bar
X: = later

It is worth mentioning that, in this method, the preceding variables cannot use the following variables, but can only use the previously defined variables. If so:

Y: = $ (x) bar
X: = foo

Then, the value of y is "bar" instead of "foo bar ".

The above are some simple variables used. Let's take a look at a complicated example, including the make function, conditional expression, and the use of a system variable "MAKELEVEL:

Ifeq (0, $ {MAKELEVEL })
Cur-dir: = $ (shell pwd)
Whoami: =$ (shell whoami)
Host-type: = $ (shell arch)
MAKE: =$ {MAKE} host-type =$ {host-type} whoami =$ {whoami}
Endif

We will talk about conditional expressions and functions later. For the system variable "MAKELEVEL", it means, if make has a nested execution action (see the previous "use make nested"), this variable records the number of calls to the current Makefile.

Next we need to know about two variables. Let's take a look at an example. If we want to define a variable whose value is a space, we can do this:

Nullstring: =
Space: = $ (nullstring) # end of the line

Nullstring is an Empty variable with nothing in it, and our space value is a space. It is difficult to describe a space on the right side of the operator. The technology used here is very useful. First, use an Empty variable to indicate the value of the variable, the "#" annotator is used later to indicate the termination of variable definition. In this way, we can define a variable whose value is a space. Please note that the usage of "#" here is worth noting for the feature of the annotator "#". If we define a variable like this:

Dir: =/foo/bar # directory to put the frobs in

The value of the dir variable is "/foo/bar", followed by four spaces. If we use this variable to specify another directory -- "$ (dir) /file.

Another useful operator is "? = ", First look at the example:

FOO? = Bar

The meaning is that if FOO has not been defined, the value of the variable FOO is bar. If FOO has been previously defined, then this language will do nothing, which is equivalent:

Ifeq ($ (origin FOO), undefined)
FOO = bar
Endif

 

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