"Linux" Makefile Usage Summary __linux

1. Makefile Introduction

Makefile is used in conjunction with the Make command.

Many large projects are compiled through Makefile, and if there is no Makefile, the dependencies between the various libraries and code in many projects are not known to be complicated.

Makefile's ability to organize processes is so strong that it can be used not only to compile projects, but also to organize some of our day-to-day operations. This requires everyone to play their own imagination.

This blog is based on {essence} with me to write Makefile and sorted, some deletions, append some examples.

1.1 Makefile Main 5 sections (display rules, obscure rules, variable definitions, file instructions, notes)

The makefile basic format is as follows:

Target ...: Prerequisites
    ... Command
    ...
    ...

where the target-destination file, either object or executable prerequisites-generates the files required for target or the target command-make the command that needs to be executed (arbitrary Shell command), the command in makefile must begin with [tab]

Display rules:: Description of how to generate one or more target files (including generated files, file dependencies, generated commands) obscure rule:: The rule variable defined by make's automatic inference function:: Makefile the variable file defined in the:: Makefile reference to the other MA Kefile; Specify the active part of the makefile; Define a multiline command comment:: Makefile only line comment "#", if you want to use or output "#" characters, you need to escape, "\#"

1.2 The way GNU make works read the main makefile (other makefile can be referenced in the primary makefile) to read the variables in the other makefile initialization files included, deduce the obscure rules and analyze all the rules for all the mesh Document creation dependency chain based on dependencies, determines which targets to regenerate execute build command

2. Makefile Primary grammar 2.1 Makefile rule 2.1.1 Rule Syntax

There are 2 main rules: dependencies and methods of generating goals.

The syntax has the following 2 kinds:

Target ...: Prerequisites
    ... Command
    ...

Or

Target ...: prerequisites; Command
    command
    ...

* Note * command is too long, you can use "\" as a line feed

Wildcard character *:: Represents any one or more characters in the 2.1.2 rule ? :: Represents any one character [...]:: Ex. [ABCD] represents any character in A,b,c,d, [^ABCD] represents a character other than A,b,c,d, [0-9] represents any number in 0~9 ~:: Represents the user's home directory

2.1.3 Path Search

When a large number of source files are involved in a makefile (these source files and makefile are most likely not in the same directory),

At this point, it is best to clear the path of the source file in makefile to facilitate the compile-time lookup. There is a special variable in the makefile VPATH that completes this function.

After VPATH is specified, if the file or dependent file is not found in the current directory, Makefile goes back to the path specified by VPATH to find it again.

VPATH usage: VPATH <directories>:: When a file is not found in the current directory, search for VPATH <pattern> <direct from <directories> Ories>:: <pattern> format files, search from <directories> vpath <pattern>:: Clear Compliant <pattern> File search path in format vpath:: Clears all file paths that have been set

# example 1-When files are not found in the current directory, in order from the SRC directory ... Find files in/parent-dir directory
VPATH src:.. /parent-dir   

# Example 2-. h files at the end of the./header directory find
VPATH%.h./header

# Example 3-Clear the rules set in Example 2 VPATH
%.h

# example 4- Clears all VPATH settings
VPATH

variables in 2.2 Makefile 2.2.1 Variable definition (= or: =)

OBJS = PROGRAMA.O programb.o
objs-add = $ (OBJS) PROGRAMC.O
# or
objs: = PROGRAMA.O programb.o objs-add
: = $ (OBJS) PROGRAMC.O

where = and: = The difference is that: = Only use the previously defined variables, = can use the variables defined later

Test =

# makefile Content
OBJS2 = $ (OBJS1) programc.o
OBJS1 = programa.o programb.o all

:
    @echo $ (OBJS2)

# Execute make in bash, which shows that although OBJS1 is defined after OBJS2, the
$ make PROGRAMA.O PROGRAMB.O can be used in advance in OBJS2 PROGRAMC.O

Test: =

# Makefile Content
OBJS2: = $ (OBJS1) programc.o
OBJS1: = PROGRAMA.O programb.o all

:
    @echo $ (OBJS2)

# in Bash execute make, you can see that $ (OBJS1) in OBJS2 is empty
$ make
PROGRAMC.O

2.2.2 Variable substitution

# Makefile Content
SRCs: = programa.c programb.c programc.c
OBJS: = $ (SRCS:%.C=%.O) all

:
    @echo "SRCS:" $ (SRCS
    @echo "OBJS:" $ (OBJS)

# Bash runs make $ make
srcs:  programa.c programb.c
programc.c objs:  PROGRAMA.O PROGRAMB.O PROGRAMC.O

2.2.3 Variable append =

# Makefile Content
SRCs: = programa.c programb.c programc.c srcs
+ = programd.c all

:
    @echo "SRCS:" $ (SRCS)

# Bash Run make
$ make
srcs:  programa.c programb.c programc.c programd.c

2.2.4 Variable Overlay override

The effect is to enable variables defined in makefile to override the variables specified in the Make command argument

Syntax: override <variable> = <value> override <variable>: = <value> override <variable> = < Value>

Below is an example to realize the function of override: