A general Makefile

We develop programs in the Linux environment and have to write Makefile by ourselves. A slightly larger project will contain many. c source files.
If we use gcc to compile each source file one by one, the efficiency will be much lower. However, if we can write a Makefile, we only need to execute a make command, this greatly improves the development efficiency.

However, Makefile has many syntax rules and lacks reference materials. For Beginners, writing is still difficult and often daunting.
Next we will introduce a more general and concise Makefile. You only need to make some modifications to it and use it in your own project.

Now suppose we have a project named my_project. The project source code directory contains five source files: app1.c, app2.c, app3.c, and main. c. Now we need to compile app1.o, app2.o, app3.o, and main. o, and then link these. o files into an executable program named my_app in ELF format. Let's first look at how to write the simplest Makefile:

My_app: main. o, app1.o, app2.o, app3.o, app4.o
Gcc-o my_app main. o app1.o, app2.o, app3.o, app4.o

Main. o: main. c
Gcc-c main. c
App1.o: app1.c
Gcc-c app1.c
App2.o: app2.c
Gcc-c app2.c
App3.o: app3.c
Gcc-c app3.c

Clean:
Rm main. o app1.o, app2.o, app3.o, app4.o

This is a silly Makefile. It is not flexible and reproducible. Imagine if there are 50 source files under our project, wouldn't it be necessary to write them one by one.

Our goal is to write a Makefile, which can be used between various projects with slight modifications.

The Makefile below meets this requirement:
SRCS = $ (wildcard *. c)
OBJS =$ (SRCS:. c =. o)
CC = gcc
Primary des =-I/×××
LIBS =-L/×××
CCFLAGS =-g-Wall-O0

My_app: $ (OBJS)
$ (CC) $ ^-o $ @ $ (DES) $ (LIBS)

%. O: %. c
$ (CC)-c $ <$ (CCFLAGS)
Clean:
Rm *. o
. PHONY: clean

It seems that this Makefile is much simpler than the previous one. Of course, it is not as intuitive as the previous one.
In fact, Makefile is written to improve our work efficiency, rather than increase our workload.

Therefore, Makefile provides many powerful functions, such as defining variables and using wildcards. You can achieve twice the result with half the effort.
Let's analyze the Makefile one by one:

SRCS = $ (wildcard *. c)
This statement defines a variable SRCS whose value is all source files ending with. c in the current directory.

OBJS =$ (SRCS:. c =. o)
Here the value of the variable OBJS is the. o target file compiled from all. c files in SRCS.

CC = gcc
Variable CC represents the compiler we want to use

Primary des =-I/×××
LIBS =-L/×××
Specify the path of the header file to be referenced and the path of the Library (××× indicates the path) in addition to the default header file and library file path of the compiler ).

CCFLAGS =-g-Wall-O0
The CCFLAGS variable stores compilation options.

My_app: $ (OBJS)
$ (CC) $ ^-o $ @ $ (DES) $ (LIBS)
My_app depends on all. o files. $ ^ represents $ (OBJS), and $ @ represents my_app.

%. O: %. c
$ (CC)-c $ <$ (CCFLAGS)
It is easy to compile all. c source code into the. o target file?
Clean:
Rm *. o
After you execute make clean, delete all. o files generated during compilation.

. PHONY: clean
Execute the rm *. o command every time you execute make clean.

This Makefile is flexible and universal. We can use it in our own project as long as we make slight changes to it. Of course, Makefile has many powerful functions that need further learning.

 

From programming tips