Analysis of implementation features of Linux based on i386 -- basic Foundation

Article title: Analysis of Linux implementation features based on i386-basic foundation. Linux is a technology channel of the IT lab in China. Includes basic categories such as desktop applications, Linux system management, kernel research, embedded systems, and open source.
Summary
?? This article discusses the features of linux on the cpu of the i386 system. This article introduces the interrupt mechanism, segment-and-page management of memory, and the hardware mechanism provided by task switching under the i386cpu protection mode, compare the differences between the specific implementation features of Linux and the i386 design intent. Describes how to set the Linux interrupt vector table, initialize the interrupt request queue, and attach a specific interrupt service program to the specified interrupt request queue. Tracking the transformation process from logical address to linear address to physical address in Linux, focusing on the page transformation from linear address to physical address, and analyzing the address transformation efficiency with the i386cpu.
Linux implementation features based on the i386 architecture
Preface
?? This article discusses the features of linux on the cpu of the i386 system. This article introduces the interrupt mechanism, segment-and-page management of memory, and the hardware mechanism provided by task switching under the i386cpu protection mode, compare the differences between the specific implementation features of Linux and the i386 design intent. Describes how to set the Linux interrupt vector table, initialize the interrupt request queue, and attach a specific interrupt service program to the specified interrupt request queue. Tracking the transformation process from logical address to linear address to physical address in Linux, focusing on the page transformation from linear address to physical address, and analyzing the address transformation efficiency with the i386cpu.
II. protection methods
?? 80386 there are two ways to work: Implementation and protection. Although the features of 80386 in the real mode are greatly improved compared with Intel's previous microprocessor, only 80386 in the protection mode can actually play a role. Under the protection mode, all 32 IP addresses are valid and can address physical space up to 4G bytes. the expanded memory segment management mechanism and the optional memory paging management mechanism are provided, it not only provides hardware support for memory sharing and protection, but also provides hardware support for implementing virtual memory. it supports multi-task, fast task switching and task protection environments; the four privileged levels and comprehensive privileged inspection mechanisms enable resource sharing, security and confidentiality of code and data, and task isolation. The Virtual 8086 approach is supported, easy to execute code 8086.
?? 1. 80386 addressing of protection methods
?? Under the protection mode, when addressing the data and programs in the extended memory, the offset address is still used to access the information in the memory, however, the CIDR block address in the protection mode is not provided by segment registers as in the actual mode, but contains a selection sub in the segment register of the original CIDR block address, used to select a descriptor in the descriptor table. The descriptor describes the location, length, and access permissions of the memory.
?? There are two descriptor tables under the protection mode: Global Descriptor Table and local descriptor table. The global descriptor table contains the segment definitions applicable to all programs, while the local descriptor table is usually used for unique applications. Each descriptor table contains 8129 descriptors, so the application can have up to 16384 descriptors at any time.
?? Each descriptor is 8 bytes long, and the maximum length of each global and local descriptor table is 64 KB.
?? 80386 descriptor format:
Here is a table
?? The base address of the descriptor indicates the starting position of the storage segment. a 32-bit base address allows the segment to start anywhere in 4 GB memory.
?? The segment boundary contains the last offset address of the segment. The 20-bit segment boundary makes the segment length between 1 kB and 1 MB or between 4 kB and 4 GB. Feature bit in the descriptor: G bit (granularity bit). If G = 0, it indicates that the segment boundary is 1_h to FFFFFH (from 0 to 1 MB). If G = 1, the limit value of a segment must be 4 kB to 4 GB in length.
?? If D = 0, the command is 16-bit, which means that the 16-bit offset address and the default 16-bit register are used. if D = 1, the command is 32-bit.
?? The access permission byte is as follows:
Tables available
P = 0 descriptor does not define P = 1 segment containing valid base address and boundary value
Priority of DPL descriptor
S = 0 system descriptor S = 1 code or data segment descriptor
E = 0 descriptor description data segment
ED = 0-segment upward scaling (data segment) ED = 1-segment downward scaling (stack segment)
W = 0 data cannot be written W = 1 data can be written
E = 1 descriptor description code segment
C = 0 ignore descriptor priority C = 1 follow descriptor priority
R = 0 code segment cannot be read R = 1 code segment can be read
A = 0 segment not accessed A = 1 segment already accessed
?? The content of the segment register during the protection mode operation:
Tables available
?? Select a sub-table from 8192 global or local descriptor tables. to access and specify the addresses of these tables, the microprocessor contains some program invisible registers. In the protection mode, these registers control the microprocessor.
?? Under the protection mode, each segment register contains an invisible area of the program, which is usually called a notification buffer. When the content in the segment register changes, the base address, boundaries, and access permissions are loaded into the invisible area of the segment register. This allows the microprocessor to repeatedly access a segment without having to query the segment descriptor table every time.
　　
Tables available
?? The base address and boundary of the global descriptor table are included in the global descriptor table register. The maximum length of a global descriptor table is 64 K, so the limit of the descriptor table is 16 bits. To make the microprocessor work and protect the mode, the base address and boundaries of the global description table must be loaded into GDTR.
　　
Tables available
?? The location of the local descriptor table is selected from the global descriptor table. To address a local descriptor table, a Global Descriptor must be created. To access the local descriptor table, you must load the selection sub-register into LDTR (local descriptor table register), just like selecting a sub-register. This option selects the sub-access global descriptor table, and loads the base address, boundaries, and access permissions of the local descriptor table into the LDTR telling buffer store.
　　
Tables available
?? The second part of the storage management mechanism of the page sharding machine. The paging mechanism operates after the segment mechanism to convert virtual addresses to physical addresses. Segment mechanism converts virtual addresses to linear addresses, while paging mechanism further converts linear addresses to physical addresses.
　　
?? The paging mechanism is controlled by the content of control registers in the microprocessor. The paging mechanism is enabled by PG bits in CRO. If PG is set to 1, the paging mechanism is enabled. PG = 0. The paging mechanism is used to directly treat the linear address generated by the segment mechanism as a physical address.
　　
　　
CR1 retained
Store the linear address of page faults in CR2
The operations on the PCD and PWT pins of the microprocessor are controlled.
If the PCD position is set, the PCD pin changes to logic 1 in a non-paging bus cycle.
Allows external hardware to control the second-level high-speed buffer memory. PWT bit
The page cycle appears on the PWT pin, used to control the speed delay of writing directly to the system
Punch memory. The base address of the page Directory (10-bit high of the page) is also contained in
Locate the page Directory of the page conversion component. This base address locates the page directory in any
Memory with 4 kB as the boundary.
?? The linear addresses generated by the software are divided into three parts: addressing page Directory items, page table items, and page offset addresses.
Linear Address: table available
?? The page directory table is stored in a 4 K page. There are a total of 1024 table items in the page Directory. each table item in the page directory is 4 bytes long and points to a page table. A 10-bit high linear address generates an index on the page directory table. The index returns the table item weight, specifying and selecting 1024 4-byte table items, each table item is used to select the corresponding physical page.
?? Page directory and page table items:
Tables available
?? The page directory and page table items are 20 characters in height and contain 20 characters in physical address, while the 12 characters in height contain the page attributes.
Tables available
?? The P bit indicates that the table entry is valid for address conversion (P = 1) or invalid (P = 0 ). An exception occurs when an invalid table item is encountered during page conversion. If P = 0, the remaining 80386 of the table items will not be explained and can be used by the software. In fact, Linux uses this method in page switching. When a page is in memory, the P-bits of the table items in the page table indicate that the page is in memory, while others indicate various properties of the page. When a page is switched to a disk, the corresponding table items no longer point to a physical page, but become a disk page, indicating the whereabouts of the page. Because the memory bit is 0 at this time, the page is no longer in memory, so the MMU unit in the microprocessor is ignored for all of them, while in the Linux kernel, it is used to uniquely determine the location of a page on the disk, including the file or device, and the location of the page in this file sink.
?? R/M this/write bit. If this bit is 1, you can read, write, or execute the page specified by the page table. if this bit is 0, the page can be read or executed, but the page cannot be written. However, the read/write bit does not always work. However, the R/M bit is ignored when the microprocessor is executed at one of the super-privileged levels (0, 1, or 2. The R/M bit in the directory table item is applied to all the pages mapped to the directory table item.
?? U/S User/system bit. If this parameter is set to 1, the page specified by the page table can be accessed by programs executed at any privileged level. If this parameter is set to 0, this page can only be accessed by a program at the super privilege level. The U/S bit in the directory table item is applied to all the pages mapped to the directory table item.
?? PMT writes directly to the bit. Control the use of write-through or write-back policies for page tables or page cache management. If this bit is 1, a write-to-cache policy is used for the page table or page. if this bit is 0, a write-back policy is used.
?? The high-speed buffer bit is disabled in PCD. If this bit is 1, the page table and page do not need high-speed cache. if this bit is 0, high-speed cache is available. When the CD bit (Cache Disable) in the CRO is set, the microprocessor ignores the PCD bit.
?? A. If this parameter is set to 1, the directed page table and Page have been accessed (read or written). Otherwise, the directed page table and Page are not accessed.
?? D indicates whether the page has been written. When the memory management mechanism calls a page into the physical memory, it resets the bit. when the microprocessor writes to it, the bit is set.
?? AVL is used by software.
?? The minimum 12-bit linear address and the last physical address are formed from the physical address (20-bit high) in the page table.
?? 2. interruption in protection mode
?? Protection methods use a group of 256 interrupt descriptors stored in the interrupt descriptor table (IDT, interrupt descriptor table) to replace the interrupt vectors in the real mode. The interrupt descriptor table is 256*8 (2 K) bytes long, and each descriptor is 8 bytes long. The interrupt descriptor table is located in any storage unit in the system by the address register (IDTR) of the interrupt descriptor table. The IDTR length is 48 characters. the 32-bit base address specifies the base address of the IDT. the 16-bit limit specifies the segment limit of the IDT. Because 80386 only supports a maximum of 256 interruptions/exceptions, the maximum length of the IDT table is 2 K and the segment limit in bytes is 7 FFH.
?? The descriptor is also called a "gate", which means that when an interruption occurs, it must be used to access the corresponding service program. However, such a door is not designed to interrupt, as long as you want to switch the running status of the CPU, that is, its priority level, for example, from level 3 of the user to level 0 of the system, you have to go through one door. The way from the user state to the system state is not only limited to interruptions (or exceptions, or traps), but also through the subroutine to CALL and transfer the command JMP to achieve the goal.
?? For different purposes and purposes, there are four types of CPUs, namely the task gate, interrupt gate, and trap gate) and call gate ). Except for tasks, the structures of the other three doors are basically the same,