The architecture of the Da Vinci digital media on-chip system and the Linux Startup Process-Linux general technology-Linux programming and kernel information. The following is a detailed description. Da Vinci (DaVinci) digital media platform TMS320DM6446/3 adopts the ARM + DSP dual-core architecture. This article introduces the hardware structure of the chip and the Startup Process of the Da Vinci DMSoC and Linux OS.
Da Vinci DMSoC hardware Overview
1. Da Vinci digital media on-chip system (DMSoC) provides two kernels (ARM + DSP) and video processing subsystem (VPSS ); multiple Boot modes (NOR Flash/NAND Flash/UART0 Boot Mode); two power domains; multiple clock trees; multiple pins independent or reusable peripherals.
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Function Structure of DM6446
● ARM-DSP Integration
For the dual-core da Vinci architecture, everyone is most concerned with the resource allocation between two cores, communication methods, and how to efficiently achieve resource sharing. ARM exclusive (DSP unavailable) peripherals include: UART0/1/2, I2C, watchdog timer, PWM0/1/2, ARM interrupt controller, USB2.0, ATA/CF, SPI, GPIO, VPSS, EMAC/MDIO, emifa control, VLYNQ, MMC/SD. Peripherals of DSP exclusive (ARM unavailable) include DSP interrupt controller and VICP. Peripherals shared by ARM and DSP include EDMA, Timer0/1, Power & Sleep Controller, ASP, and EMIFA Data.
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ARM-DSP Integration Structure
As shown in figure 2, we can clearly see that ARM can access DSP in-chip memory (L2RAM and L1P/D); DSP can access ARM in-chip memory; ARM and DSP share DDR2 and AEMIF. Therefore, generally, ARM only needs to pass the data address pointer to the DSP, instead of moving large data blocks. Communication between ARM and DSP can be achieved through mutual interruption. ARM can interrupt the DSP (through four general interrupt and one unshielded interrupt); DSP can interrupt the ARM through two general interrupt. ARM controls the power supply, clock, reset, and boot of the DSP.
● DMSoC memory ing
Da Vinci DMSoC multiple on-chip memory is related to two processors and different subsystems. To simplify software development, all the memory in the DMSoC is centrally stored, as shown in table 1.
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● DMSoC exchange center Resources
We can see that DMSoC has abundant peripherals and video processing hardware resources, and ARM and DSP share DDR2 and other memory resources, then, how does DMSoC ensure that ARM, DSP, and VPSS do not cause conflicts when accessing peripherals or memory resources at the same time? The Exchange Center Resource (SCR: Switched Central Resource) in DMSoC is managed. 3. Call any source that initiates data transmission as the Master (each Master has a dedicated ID). The destination to be accessed by this Master is called Slave, in this way, a data transmission path is formed between the Master and Slave. We can see that there are many parallel Master-to-Slave data paths in the SCR. If it is a different Master and the same Slave, you can set the priority of each Master to get the best performance of the special application system. For most masters, their priority can be set through MSTPRI0 and MSTPRI1. If the Master is C64x +, VPSS, and EDMA, you can control their own priorities through their own registers, so that you can implement high video data throughput bandwidth more flexibly and quickly. For more information, see the data manual of DM6446.
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Structure Diagram of DMSoC switching center Resources
Power Supply and reset
Da Vinci DMSoC has two power domains: The Always On domain and the DSP domain. The Always On field is powered by the cvdd arm core and provides power to ARM, bus, SCR, and all peripherals except VICP. The DSP power field is powered by the CVDDDSP core, provide power to DSP and VICP.
The power consumption of the dual-core architecture da Vinci DMSoC is also very competitive. On the one hand, it depends on the chip technology, and on the chip internal clock and power structure. As shown in figure 4, da Vinci DMSoC provides a Power & Sleep Controller to manage the chip Power switch and reset. Software can be used to control the DSP power supply domain and to control the switch and reset of the DSP and Its module clock. PSC does not support power failure control of ARM and Its modules, local ARM reset, and clock shutdown control of ARM. Meanwhile, PSC can interrupt ARM and DSP and support the emulation feature of IcePick.
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Power sleep controller of DM6446
For details about the reset type, trigger source, and Reset object of da Vinci DMSoC, see table 2.
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Da Vinci DMSoC initialization process
● Da Vinci DMSoC reset status
After a power-on reset of DM644x, most modules on the chip are not working. The PLL is in the Bypass mode. The status of the DSP subsystem depends on the DSP_BT pin. The status of UART1 and UART2 is also not working. The status of UART0 depends on the BTSEL pin (if BTSEL = 11, UART0); EMIFA is in the working state, and its data bus width is determined by EM_WIDTH, and the address bus width is determined by AEAW. Most pins of the chip are configured as GPIO pins. Pin multiplexing is controlled by registers PINMUX0 and PINMUX1.
● Da Vinci DMSoC initialization sequence
(1) reset DMSoC. The chip configuration is determined by PSC and depends on the status of BTSEL [0-3], EM_WIDTH, AEWA, and DSP_BT.
(2) ROM boot loader (if selected ). NAND or UART0 initialization.
(3) Boot-loading ). Taking U-boot as an example, ① enable the power field: DDR2 and DSP; ② set the clock frequency (multiplication and division coefficients of the ARM, DSP, and DDR2 clock); ③ set the pin multiplexing controller; ④ set up ARM boot to start the operating system.
(4) Start the operating system. Taking Linux as an example, ① initialize ARM; ② initialize the hardware system; ③ initialize the Linux environment.
● U-boot initialization sequence
Generally, ARM Linux requires a little initialization for boot loader. The dvevm of ti currently uses a U-boot-1.1.3. U-boot code first runs u-boot/cpu/arm926ejs/start. s, chip and some DVEVM board hardware configuration mainly in u-boot/board/davinci/platform. S and davinci. c. U-boot/board/davinci/platform. S sets the most basic system hardware environment, including system PLL and DDR2 initialization, PSC configuration and enable UART0, AEMIF and other hardware modules. The Da Vinci board designed by some engineers may use Flash different from DVEVM, so u-boot/board/davinci/Flash. c should be modified according to the flash parameters used. For more information about the NAND Flash IDs supported by DM644x, see the relevant documents of the DM644x DMSoC.
Taking NOR Flash boot as an example, DVEVM u-boot initializes the following da Vinci DMSoC content:
(1) Guanzhong disconnection and MMU.
(2) Enable the DSP power field (PTCMD) to reset the DSP.
(3) initialize the PLL, enable DDR2, soft reset DDR2, and re-enable DDR2, so that it is out of the reset state.
(4) initialize the system PLL.
(5) configure the AEMIF pin as the NOR Flash interface.
(6) VTP calibration.
After completing the preceding steps, U-boot is ready to boot ARM Linux.
(1) configure the system memory (via ATAG _ MEM block and mem =) NAND Flash and DDR2.
(2) load the kernel to the specified storage address through loading methods such as TFTP.
(3) load the RAM Disk if defined.
(4) initialize the boot parameters passed to the kernel (EMAC address, serial port, console, video format, etc)
(5) obtain the value of the ARM Linux server type (DVEVM: #901 ).
(6) set the kernel tagged list.
(7) set ARM registers with initial values.
(8) Call the kernel.
● Linux Initialization steps
(1) the Linux kernel needs to obtain the following parameters from the boot loader (U-boot.
* The initialized memory system.
* R0 = 0; R1 is an ARM Linux server type value.
* R2 points to the ATAG struct: ① physical memory area; ② whether to use ram disk and Its compressed version address; ③ specific initialization parameters of the video driver; ④ kernel command line; ⑤ other parameters (Serial Port and version number ).
