Arm mmu source code analysis, armmmu source code

Arm mmu source code analysis, armmmu source code

The mmu module is provided in the arm7 and later versions. This module can remap addresses in units. This is a module that extends the address space and increases code flexibility. The following is a source code

Void rt_hw_mmu_init (struct mem_desc * mdesc, rt_uint32_t size)
{

unsigned int i;    unsigned int reg;    unsigned int low,high,ram;    low = (0xa1000000 - 0xa0000000)>>20;    high = (0xfffffffff - 0xa1000000)>>20;    ram  = (0x20000000 -0x10000000)>>20;    for(i=0;i<low;i++){    reg = 0x10000000 +(i<<20);    reg +=   0xc12;    *(int *)(0xa1000000 +i*4) =reg;    }    for(i=0;i<ram;i++){    reg = 0x10000000 +(i<<20);    reg +=   0xc12;    *(int *)(0xa1000000+(0x10000000>>20)*4 +i*4) =reg;    }    for(i=0;i

}
In the initial stage, we need to create an address ing table, which allows the cpu to access the Address requested by the code to address the address. The address obtained in this table is the real physical address. The request address from our code to the cpu has now become a virtual address, which must be converted once through mmu. In this way, multiple virtual addresses correspond to one physical address, and one shared memory can be implemented by hardware. This table should look like this.
00000c12 00100c12 00200c12 00300c12 .....
It can be seen that this is a ing of the first-level page table, and its unit is 1 M address ing.
0 ---- 0000
1 m ----> 1 M
Here is a ing relationship of the original address.
If yes
00100c12 0 address in this table
0 --- "1 M zero address corresponds to 0x100000 address. At this time, we access 0 address and actually get the N content of 0x1OOOOO address.
Void mmu_setttbase (register rt_uint32_t I)
{
Register rt_uint32_t value;

value = 0;asm ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));value = 0x55555555;asm ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));asm ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));

}

After the initialization of the entire table is completed, the first address of the table is told to the cpu, that is, the assembly code of the coprocessor above. For details, refer to the official arm documentation.
Note: the address of this table cannot be mapped to other places. It must be the address of the coprocessor. Otherwise, the table cannot be found by the cpu, your address cannot be found.
The mmu is enabled, and the cpu is notified not to directly send the address but to mmu for conversion,
Void mmu_enable ()
{
Register rt_uint32_t I;

/* read control register */asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));i |= 0x1;/* write back to control register */asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));

}
A bit is also set for the compilation of coprocessor.
Cache is performed later.

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