ARM9MMU, ARM9MMU

ARM9MMU, ARM9MMU

One-page table

1. A page table is a data segment placed in RAM (generally DRAM.

2. The ARM address space is 2 ^ 32 bytes, that is, 4G bytes.

3. There are a total of 4096 records in the level-1 page table. The address block corresponding to each record is 1 MB. The records in the level-1 page table divide the virtual continuous 4G addressing space.

4. The content of each record in the level-1 page table is the physical address of the virtual 4G addressing space. For example:

A. Set the base address of a level-1 page table to 0x31000000. The base address starts with the base address, and the subsequent 4096*4 bytes correspond to the level-1 page table.

B. The first-level page table records 0 x 0th 0 ~ of the virtual address ~ 0x000F, FFFF, 1st records correspond to 0x0010,000 0 ~ of the virtual address ~ 0x001F, FFFF, and so on.

C. Correspondingly, the content of the first-level page table's 0th records (12-bit high) corresponds to the virtual address 0x0000,000 0 ~ 0x000F, FFFF physical address (base address), 1st records (12-bit high) corresponding to virtual address 0x0010,000 0 ~ 0x001F: the physical address (base address) of FFFF. The low position in each record contains the permission access control bit.

Binary TLB (Translation Lockaside buffer): Fast table

A quick table can be understood as the cache of a page table. A page table is a piece of data in RAM, which has a high access latency. Loading adjacent page tables to the quick table can greatly accelerate the MMU merging address.

Tri-Cache

To be continued...

 

 

 

 

 

N about MMU startup

If the page table is set to virtual address = physical address, the code running, data storage, and stack are not affected after MMU is enabled, and the code continues to run correctly.