Basic architecture of mobile terminal baseband chip

(i) Overview

The baseband digital processing function and the basic peripheral function of the handset are all concentrated on the monolithic system (SOC). The basic architecture of the microprocessor + Digital signal processor (DSP) structure, microprocessor and DSP processing capacity has been enhanced. The microprocessor is the control center of the whole chip. Executes a real-time embedded operating system (such as nucleus PLUS). DSP subsystem is the focus of baseband processing, including a lot of hardware accelerator and baseband dedicated processing module, complete the physical layer functions.

Today, with the development of real-time digital signal processing technology, the arm microprocessor (using different micro-series, such as 3G chip multi-ARM9), DSP and FPGA architecture become the main way to realize the mobile terminal chip. is a typical logic architecture of baseband chip based on ARM architecture, in which 3g/4g baseband logic refers to DSP operating subsystem.

Figure 1 Baseband chip framework on a typical ARM architecture

Microprocessor through RTOS (such as nucleus PLUS) completed multitasking scheduling, inter-mission communication, peripheral driver, microprocessor and DSP subsystem and other modules of communication and so on. Features also include:

1, the entire mobile station control and management, including timing control, digital system control, RF control, power-saving control and so on.

2. Complete software functions, namely the Wireless Communication Protocol physical layer and protocol stack communication, high-level protocol stack (TCP/IP, etc.), if used in the function machine will also include MMI (Man-machine Interface) and application software.

The DSP subsystem is used to deal with all the algorithms in the physical layer. The channel encoding, encryption, channel equalization, Speech encoding/decoding, modulation and demodulation are included in the information. The data communication between DSP subsystem and microprocessor subsystem includes dual port random read memory (RAM), multi-bus shared resource (some vendors adopt Amba's Multilayer bus protocol), etc. Multi-mode multi-band baseband chips may contain multiple DSPs.

In the memory organization, the microprocessor and DSP subsystem may have their own separate fast buffer memory (Cache), with shared on-chip SRAM and shared external expansion memory.

Extended memory generally supports synchronous dynamic random memory (SDRAM) and NAND flash RAM.

The FLASH ROM can be used to store the boot ROM, link operating system, and user application's CP ROM. The ROM interface is primarily used to connect the memory Flash ROM of the stored program. The RAM interface is primarily used to connect the static RAM (SRAM) that stores the staged data.

On-chip embedded large-capacity static random read memory (SRAM) is very common, which helps to reduce power consumption. Reduce system costs.

Intel also has embedded large-capacity flash memory (Flash RAM).

Peripherals and interfaces. Baseband chips often support multiple interfaces to facilitate and apply processor communication and add other modules such as WiFi, GPS. The interface includes UART, multimedia Interface (MMI), Universal Serial Bus (USB), SPI, etc. The MCU communicates with the external interface via DMA, the destructors band Chip does not have integrated RF, and the RF dedicated interface.

(ii) traditional ARM baseband chip basic framework

The Tanmoki band Chip uses a dual-core architecture, an ARM processor and a DSP. The communication between the two is performed via a dual-port static memory (Dual port SRAM).

At the same time, ARM will also do some direct control of the DSP subsystem, through the direct operation register (address/control/data register) completed. Of course, multi-mode baseband can also be implemented for some dsp,1 arm+1 dsp+ multiple accelerator subsystems that are more computationally capable.

2 is the architecture of the traditional dual-core baseband chip, in which the blue single line represents the direct control of the arm to the DSP subsystem.

Figure 2 Traditional baseband chip master architecture

Two-port SRAM for ARM and DSP subsystem data interaction reasons are: (1) Two subsystems of the clock is usually inconsistent, SRAM can do good bridging, (2) SRAM data bandwidth is large, low power consumption.

In the implementation process should pay attention to read, write synchronization problem, prevent two subsystems to the same block of data read and write at the same time. By setting a semaphore control, a party may not write (read) while reading (writing).

(iii) Multimode baseband basic frame

The multi-mode mobile terminal baseband chip becomes a must, finally on a baseband chip to support all the mobile network and wireless network format, including 2G, 3G, 4G and WiFi, etc. Multi-mode mobile terminals enable seamless roaming between multiple mobile networks and wireless networks around the world. A variety of communication patterns in a chip will be greatly added to achieve the difficulty of the chip, not only to design a common mobile communication mode implementation platform. Also in the limited size range for each communication mode to add a specific accelerator unit, MCU and the different mode subsystem is also to consider the mode switching must be the communication management. The complexity of the software on the MCU becomes higher. There is a need for direct exchange of data between different mode subsystems because of the need to share some data, such as the base station signal strength.

In this section, we describe the logic architecture of multimode baseband chip with the basic architecture of GSM/EDGE/TD-SCDMA three mode baseband chip as an example. The three die chip is also a ARM9, two DSP subsystem implementation. The communication between arm and two DSP subsystems is still seen by the two-port sram,3.

Figure 3 GSM/EDGE/TD-SCDMA Three mode baseband chip block diagram

Because the Gsm/edge physical layer algorithm is basically the same, the modulation mode of the two are different (GSM adopts Gmsk, Edge 8PSK) But the Demodulation method is consistent-Viterbi decoding, so the two physical layer processing shared a DSP plus some additional hardware support. The physical layer algorithm of TD-SCDMA has a very big gap with Gsm/edge, there is a completely different implementation system, especially TD-SCDMA joint detection algorithm needs a lot of calculation. Therefore, the independent DSP subsystem is required to implement.

A major technical point of the Multimode terminal is the switching of the communication mode. This requires baseband chip support. It is easier to switch modes manually. Different models of the DSP subsystem are independent, simple bundle, MCU in different modes of the protocol stack is also created independent task can be. Manual switching in real-world business that would be ruthlessly discarded by the user, so the Multimode terminal must be able to intelligently explore the different modes of signal strength. Self-active completion mode switching, it is best to be in the user can not feel the situation. Multimode baseband mode of self-active switching requires additional design difficulty, need to be a multi-mode protocol stack tightly, the respective physical layer between the necessary data communication. The specification and algorithm of the mutual switching of various communication modes makes the combination of multiple mode protocol stacks on the MCU known as possible, and the physical layer information sharing can be done by establishing simple direct connection (such as register or SPI) between different DSP subsystems.

If all the communication modes are encapsulated on one chip. Mode switching is relatively straightforward when controlled by a master processor. The only one that can achieve single-chip support for full-mode is the Qualcomm. Most end baseband solutions are composed of two or more baseband chips, such as the CDMA/GSMG baseband +lte baseband. The two baseband chips communicate via SPI,SDIO,USB.

Basic architecture of mobile terminal baseband chip