Basic architecture of mobile terminal baseband chip

(i) Overview

Baseband digital processing functions and basic peripheral functions of mobile phones are concentrated on the single chip system (SOC), the basic architecture of the microprocessor + Digital signal processor (DSP) structure, microprocessor and DSP processing capacity has been enhanced. The microprocessor is the control center of the entire chip and runs a real-time embedded operating system (such as nucleus PLUS). DSP subsystem is the focus of baseband processing, which contains many hardware accelerators and baseband dedicated processing modules to complete all physical layer functions. Now, with the development of real-time digital signal processing technology, the ARM microprocessor (will adopt different micro-series, such as 3G chip multi-ARM9), DSP and FPGA architecture become the main way to realize the mobile terminal chip. It is a typical logic architecture of baseband chip based on ARM architecture, in which 3g/4g baseband logic refers to DSP operating subsystem.

Figure 1 Baseband chip framework on a typical ARM architecture

The microprocessor uses RTOs (such as nucleus PLUS) to accomplish multitask scheduling, inter-mission communication, peripheral driver, and communication between microprocessor and DSP subsystem and other modules, etc. Features also include:

1, the entire mobile station control and management, including timing control, digital system control, RF control, power-saving control and so on.

2, complete all the software functions, namely the Wireless Communication Protocol physical layer and protocol stack communication, high-level protocol stack (TCP/IP, etc.), if used in the function machine will also include MMI (Man-machine Interface) and application software.

The DSP subsystem is used for the processing of all the algorithms in the physical layer, including channel coding, encryption, channel equalization, Speech coding/decoding, modulation and demodulation. The data communication methods between DSP subsystem and microprocessor subsystem include dual-port random Read memory (RAM), multi-bus shared resource (some vendors adopt Amba's Multilayer bus protocol), etc. Multi-mode multi-band baseband chips may contain multiple DSPs.

In the memory organization, the microprocessor and DSP subsystem may have their own independent cache memory (cache), with shared on-chip SRAM and shared external expansion memory. Extended memory generally supports synchronous dynamic random memory (SDRAM) and NAND flash RAM. The FLASH ROM can be used to store the boot ROM, link operating system, and user application's CP ROM. The ROM interface is primarily used to connect the memory Flash Rom,ram interface of the storage program to the static RAM (SRAM) that stores the staged data. On-chip embedded large-capacity static random read memory (SRAM) is very common, to reduce power consumption and reduce system costs. Intel also has embedded large-capacity flash memory (Flash RAM).

In terms of peripherals and interfaces, baseband chips often support multiple interfaces to facilitate and apply processor communication and add other modules such as WiFi, GPS. The interface includes UART, multimedia Interface (MMI), Universal Serial Bus (USB), SPI, etc. The MCU communicates with the external interface via DMA, the destructors band Chip does not have integrated RF, and the RF dedicated interface.

(ii) traditional ARM baseband chip basic framework

The Tanmoki band Chip uses a dual-core architecture, an ARM processor and a DSP, and the communication between the two is performed via a dual-port static memory (Dual port SRAM). At the same time, ARM will also do some direct control of the DSP subsystem, through the direct operation register (address/control/data register) completed. Of course, for some computing ability than the strong dsp,1 a arm+1 dsp+ multiple accelerator subsystem can also achieve multimode baseband.
2 is a traditional dual-core baseband chip architecture diagram, wherein the blue single line represents the direct control of ARM to the DSP subsystem.

Figure 2 Traditional baseband chip master architecture

Two-port SRAM for ARM and DSP subsystem data interaction reasons are: (1) Two subsystems of the clock is usually inconsistent, SRAM can do good bridging, (2) SRAM data bandwidth is large, low power consumption. In the implementation process, we should pay attention to the synchronization problem of reading and writing, and prevent two subsystems from reading and writing the same block data simultaneously. The other party may not write (read) when one reads (writes) by setting a semaphore control.

(iii) Multimode baseband basic frame

Multi-mode mobile terminal baseband chip is inevitable, that is, finally on a baseband chip to support all mobile network and wireless network format, including 2G, 3G, 4G and WiFi, etc., Multimode Mobile terminal can achieve a global range of mobile networks and wireless network between the seamless roaming. A variety of communication modes in a chip will greatly increase the difficulty of the chip, not only to design a common mobile communication mode to achieve the platform, but also in a limited size range for each communication mode to add a specific accelerator unit, MCU and different mode subsystem should also consider the mode switch must be the communication management. The complexity of the software on the MCU becomes higher, and it is necessary to exchange some data directly between different mode subsystems because of sharing some data (such as base station signal strength).

This section describes the logic architecture of the multimode baseband chip with the basic architecture of the GSM/EDGE/TD-SCDMA three mode baseband chip. The three die chip is another ARM9, two DSP subsystem implementation, ARM and two DSP subsystem communication between the two sram,3 is still shown.

Figure 3 GSM/EDGE/TD-SCDMA Three mode baseband chip block diagram

Because the Gsm/edge physical layer algorithm is basically consistent, the two modulation methods are different (GSM uses GMSK, Edge 8PSK) But the Demodulation method is consistent-all Viterbi decoding, so the two physical layer processing shared a DSP plus some additional hardware support. The physical layer algorithm of TD-SCDMA is very different from that of Gsm/edge, and there are a lot of implementation systems, especially the joint detection algorithm of TD-SCDMA, which needs a large number of computations, so it needs independent DSP subsystem.

A major technical point of the Multimode terminal is the switching of the communication mode, which requires baseband chip support. If the manual switching mode is relatively simple, the different modes of the DSP subsystem are independent, simple bundle, MCU in different modes of the protocol stack also create tasks independently. Actual commercial manual Switching that is the user will be ruthless abandon, so the multimode terminal must be able to intelligently detect the signal strength of different modes, automatic completion mode switching, it is best to do in the user can not feel the situation. Multi-mode baseband mode automatic switching requires additional design difficulties, the need to mix multiple modes of protocol stack tightly, the respective physical layer between the necessary data communication. The specification and algorithm of the mutual switching of various communication modes makes the combination of multiple mode protocol stacks on the MCU known as possible, and the physical layer information sharing can be done by establishing simple direct connection (such as register or SPI) between different DSP subsystems.