Dual Stack mechanism of Cortex-M3

Dual Stack mechanism of Cortex-M3

The CM3 stack is divided into two types: the master stack and the process stack.

So, under what circumstances are these two stacks used?

At this time, let's take a look at the CONTROL register (CONTROL) of CM3: the CONTROL register is used to define the privileged level and to select the stack pointer currently used.

CONTROL [1]

In handler mode of Cortex-M3, CONTROL [1] is always 0. In thread mode, it can be 0 or 1.

This bit can be written only in privileged thread mode, and cannot be written in other cases. Change the Processor Model

Method: When an exception is returned, you can change the LR bit 2 to implement mode switching.

In the uC/OS-II is the LR bit 2 to switch the stack mode, in fact we also mentioned in the previous article, is the PendSV_Handler_Nosave in this command orr lr, LR, #0x04 assigns a bit of 2 to 1. In this way, the PSP is switched back when an exception is exited. Then, the task can be switched over.

The first action to respond to an exception is to automatically save the necessary part of the site: In turn, xPSR, PC, LR, R12, and R3-R0 are automatically pushed into the appropriate stack by the hardware: if the current code is using PSP when an exception is returned, press PSP to use the thread stack. Otherwise, press MSP to use the master stack.

Remember that the CPU will always use the primary stack (MSP) once the service is interrupted ).

UC/OS-II task, also known as its thread, using the stack is PSP, low-priority task to high-priority task switching is also completed by PSP.

When the developed program is relatively simple (CM3 does not run the system), only MSP can be used from start to end. At this time, you only need to ensure that a stack with a large capacity is opened, and then initialize the MSP to its top-this is also the most common practice of Single Chip Microcomputer Development.