32-bit 16-bit 8-bit register and number, 16-bit 8-bit register

32-bit 16-bit 8-bit register and number, 16-bit 8-bit register
Code 32-bit, 16-bit, and 8-bit
0 EAX accumulate register AX AL
1 ECX count register CX CL
2 EDX data | base address DX DL
3 ebx bx bl 0-3 low position
4 ESP 4, 5: Stack SP AH
5 EBP BP CH
6 ESI 6, 7: pairs of string SI DH
7 EDI operation di bh 4-7 high
8. EIP address
9. flags during Eflags execution
Identifier


Remember the register encoding is useful for hard encoding in the future ......
How is the address of the 32-bit computer register determined? Is it the same as 16-bit? How should I determine the memory address?

XOR is cleared first. 32-bit and 16-bit are the same. For example, the EAX register is a 32-bit register, and AX indicates a low 16-bit register, while AH and AL indicate a low 8-bit and a high 8-bit respectively. You may not clear it. 32-bit registers are 16-bit compatible. Only a few registers are added, the segment registers are increased to eight, and the addressing bus is increased.

What are the 8-bit and 16-bit registers in a 16-bit CPU?

Take 8086 as an example. Found the following.

8086 has 14 16-bit registers, which can be divided into (1) General registers, (2) instruction pointers, (3) Mark registers, and (4) according to their purposes) class 4.
(1) There are eight General registers, which can be divided into two groups. One is the data register (4), and the other is the pointer register and address register (4 ).
Data registers are divided:
AH & AL = AX (accumulator, all I/O commands use this register to transmit data with external devices.
BH & BL = BX (base): base Address Register, often used for address index;
CH & CL = CX (count) used as an implicit counter in string processing commands.
DH & DL = DX (data): a data register, often used for data transmission.
These four 16-bit registers can be divided into 8-bit high: AH, BH, CH, DH. and 8-bit low: AL, BL, CL, DL. These two groups of 8-bit registers can be respectively addressable and used separately.
The other groups are pointer registers and address change registers, including:
SP (Stack Pointer): A Stack Pointer that can be used with SS to point to the current Stack position;
BP (Base Pointer): Base address Pointer register, which can be used as a relative Base address location of SS;
SI (Source Index): the Source address change register can be used to store the Source address change pointer relative to the DS segment;
DI (Destination Index): the Destination address change register, which can be used to store the Destination address change pointer relative to the ES segment.
These four 16-bit registers can only perform access operations based on 16 bits. They are mainly used to form the address of the operand and to calculate the valid address of the operand in stack operations and address change operations.
(2) Instruction Pointer IP (Instruction Pointer)
The IP address of the instruction pointer is a 16-bit special register that points to the Instruction byte to be retrieved. When BIU extracts an Instruction byte from the memory, the IP address is automatically added with 1, point to the next Instruction byte. Note that the IP Address points to the Address Offset within the instruction Address segment, also known as the Offset Address or valid Address ).
(3) Flag Register FR (Flag Register)
8086 has an 18-Bit Flag register FR. In FR, 9 bits are meaningful. 6 bits are status bits and 3 bits are control bits.
OF: overflow flag OF indicates whether the result OF the addition or subtraction operation OF the number OF symbols overflows. If the calculation result exceeds the range expressed by the current number OF BITs, it is called overflow. The value OF is set to 1. Otherwise, the value OF is cleared to 0.
DF: The direction sign (DF) is used to determine the direction in which the pointer register is adjusted when the string operation command is executed.
IF: indicates whether the if bit is used to determine whether the CPU responds to the interrupt request that can be blocked outside the CPU. However, no matter what the value of this sign is, the CPU must respond to the interrupt requests from the outside of the CPU that cannot be blocked and the interrupt requests generated inside the CPU. The specific provisions are as follows:
(1) When IF = 1, the CPU can respond to the interrupt requests externally blocked by the CPU;
(2) When IF = 0, the CPU does not respond to the interrupt requests that can be blocked outside the CPU.
TF: The trace flag TF. This flag can be used for program debugging. The TF flag does not have specific instructions to set or clarify.
(1) If TF = 1, the CPU is in the single-step command execution mode. At this time, each command is executed, displays the current value of each register in the CPU and the next instruction that the CPU will execute.
(2) If TF = 0, the instance is in continuous mode.
SF: Symbol sign SF is used to reflect the symbol bit of the calculation result. It is the same as the highest bit of the calculation result. In the microcomputer system, the signed number adopts the complement representation. Therefore, the SF is also... the remaining full text>