Android Camera (ii): Camera operating principle, s5pv310 camera interface (CAMIF)

First, the camera working principle

In the previous article we talked about the composition of the camera module, working principle, as a kind of understanding. Let's analyze how the camera works from the register angle. How to read the camera spec (use key parameters for driver tuning, take GT2005 as an example).

The specification, which is the description of a device, is accurate to every detail of the device, the register that the software cares about, the electrical characteristics that the hardware cares about, the package, and so on. In terms of driving alone, we just look at what works for us and we don't have to read it all. The main information is all the birds (En), all read on one hand time will be used more, find the key place on the line.

1, the overall camera is as follows: the control part for the camera power, IIC control interface, the data output for the camera shot to the master chip, all to have data, line-field synchronization and clock number. The gt2005/gt2015 is a CMOS interface image sensor chip that senses external visual signals and converts them into digital signals and outputs.

We need to provide a clock to the camera via MCLK, reset is the reset line, and the PWDN should always be low when the camera is working. The PCLK is the pixel clock, the href is the line reference signal, and the VSync is the field synchronization signal. Once the camera is provided with a clock, and the camera is reset, the camera starts to work and transmits the digital image signal synchronously via Href,vsync and PCLK. The data is sent in parallel via the D0~d7 eight data lines.

(1), Pixel Array

The GT2005 array size is 1268 columns, 1248 rows, valid pixels are 1616 columns, and 1216 rows. This means that when the camera is 1600x1200, the pixel points are more than this, remove the edge part, to ensure the image quality bar.

(2), IIC This needless to say, the camera register initialization data are transferred from here, all of the IIC devices are the same work, to the map bar, behind the detailed analysis;

The following section is important in the debug-driven process:

(3), MCLK

Electronic components work all need a clock bar, the camera to work, this is the clock we want, in the main control chip provided, this clock must have, otherwise the camera will not work.

(4), the upper and lower power sequence , this to be connected to the specification book, PWDN, Resetb these two feet, different cameras are not the same, this figure is the power sequence, the power-on reference, know where to look on the line;

(5) PCLK \d1~d7

The camera gets the data to come out, to have the data, of course, the data comes out to have clock and synchronization signal, look at its timing, and LCD display timing, the same reason is the same:

(6), the main register: resolution, YUV sequence, x-axis, y-axis mirror phase, flip

After the completion of the work, there may be some problems, the resolution is too small, the YUV sequence is not correct image, XY image direction. After the completion of these work, if there are any details of the problem, if you want to spend time, look at the specifications of the register can be solved, if you do not want to see, find the Module factory FAE, they are professional, will help you fix it soon.

(7), the hardware interface of the camera

Second, the hardware interface on the camera master chip on the s5pv310

1, camif Camera Interface

First look at the camera Interface Block diagram: (this looks a bit like, we put here, first understand, in fact, the driver is generally not involved here, but we have analyzed here, brought this out)

(1), the main properties of the camera interface:

A, support a variety of input interface: (is the above we see the four mode)

DMA (AXI 64-bitinterface) mode;

MIPI (CSI) mode;

ITU-R BT 601/656/709 mode;

Direct FIFO (PlayBack) mode;

b, support multiple output modes:

DMA (AXI 64-bitinterface) mode;

Direct FIFO mode;

C, support digital zoom digitally zoom in (DZI) capability;

D, support multi-camera input;

E, support video synchronization signal polarity programmable control;

F, support the maximum input resolution of 8192x8192;

G, support image Flip (x-axis, y-axis mirror phase, 90, 180, 270 flip);

H, support a variety of image formats;

I, support capture frame control;

J, supported image effects.

2. FIMC Fully interactivemobile Camera

The data collected by the camera are not directly processed by the CPU, and the camera controller is integrated into the main control chip, called FIMC (fullyinteractive Mobile camera). The camera needs to pass the image data to the controller, which is processed by the controller (after clipping and then previewing or coding directly) and then handing it over to the CPU. Actually the clock (MCLK) required for the camera to work is also provided by FIMC.

The camera interface on the s5pv310 is a FIMC (fully interactive mobile camera interface) that supports Itur bt-601-605 standard, AMX interface, MIPI interface

MIPI, ITU, AMX

(1), ITU International Telecommunication Union Radio Communication Sector Itu-rradiocommunication Sector of ITU referred to as ITU-R ITU-Rbt.601 16-bit data transmission, Y, U, V signal simultaneous transmission, is the parallel data, the row field synchronous output separately.
ITU-R bt.6568/10-bit data transmission, no synchronization signal required, serial data transmission, transmission rate is 601 twice times, first pass y, then pass UV. The line-field synchronization signal is embedded in the data stream.

(2), MIPI (Mobile industry processor interface) is mobileindustry Processor Interface abbreviation MIPI specification: Camera workgroup: MIPI camera Serial Interface 1.0specification. Camera Serial Interface 2 v1.0 (CSI-2)

(3), AMX (Advanced extensible Interface) is a bus protocol, which is proposed by arm company Amba (microcontroller Busarchitecture) The most important part of the 3.0 protocol is an on-chip bus for high performance, high bandwidth, and low latency.

3. Interface information

The FIMC signal definition is as follows (YCbCr mode)

Signal	/ o	Description	Type
Href	I	Line Sync Signal
PCLK	I	Pixel clock
DATA[7:0]	I	Pixel data
FIELD	O	Field signal
MCLK	O	System clock Signal

The CAM_MCLK gives the camera a clock, the RST is the reset line, and the PWDN should always be low when the camera is working. The href is the line reference signal, the PCLK is the pixel clock, and the VSync is the field synchronization signal. Once the camera is provided with a clock, and the camera is reset, the camera starts to work and transmits the digital image signal synchronously via HREF,PCLK and VSync. The data is sent in parallel via the Data0~data7 eight data lines.

4. Working sequence of different interface modes

ITU-R BT 656 input timing diagram, in which the synchronization signal is embedded in the video data, so no additional line and frame synchronization signals are required.

The ITU-R BT 601 input timing diagram, in which the downlink and frame synchronization signals are independent of the video data, therefore require a synchronous signal.

(ITU-R BT 601:16-bit data transmission; 21 cores; Y, U, v signals are simultaneously transmitted.)
ITU-R BT 656:9-core, no synchronous signal required, 8-bit data transmission, serial video transmission, transmission rate is 601 twice times, first pass y, then pass UV. ）

Delay parameters of synchronous signals

ØT1: Indicates vsync before and after insertion cycle

Øt2: Indicates the href pre-insertion cycle

Øt3: Indicates href width

ØT4: Indicates an href post insertion cycle

5. Camera clock domain, three clocks: System clock, PCLK, MCLK

Each camera interface includes three clock domains, each clock domain is the system bus clock, the second is the camera pixel clock pclk, and the third clock domain is the internal clock mclk. The system bus clock must be higher than PCLK and the CAM_MCLK must have a fixed frequency divider, such as a PLL clock. If there is an external clock oscillator, the CAM_MCLK is empty. No synchronization mmclk,pclk should be connected to the schmitt-triggered level shifter.

6. Hardware interface Circuit

Interface on the master chip:

Camera interface

Android Camera (ii): Camera operating principle, s5pv310 camera interface (CAMIF)