PCI Express (iii)-A story of packets, stack and network

Original source: http://www.fpga4fun.com/PCI-Express3.html

packetized transactions

PCI Express is a serial bus. Or is it? From the computer ' s perspective, it's a conventional bus where read and write transactions can be achieved.

The trick is and all operations are packetized. Let's assume the CPU wants to write some data to a device. It forwards the order to the PCI Express Bridge which then creates a packet. The packet contains the address and data to being written and is forwarded serially to the targeted device, which De-packetiz Es the Write order and executes it.

All operations are based on the packet, the CPU wants to write data to the device, it first sends the command to the Pci-e Bridge, the Pci-e Bridge to create the packet, the package contains the address and data, and then sent to the target device, the target device to unpack and execute the command.

What if the CPU wants to read? Same thing, the bridge forwards a packet to the targeted device, which now have to execute the read, create a return packet and send it to the bridge.
All that's pretty straighforward to does in practice thanks for the ...

The PCI Express stack

Getting packets flowing reliably along the wires takes some magic. As packets is transmitted serially at very high speed, they has to is de-serialized/assembled, decoded at the Destinatio N (remove the 8b/10b encoding), de-interleaved (if multiple lanes is used), and checked against line corruption (CRC CHEC KS).

Sounds complicated? It probably is. The thing is, we don ' t really care because most of the complexity are handled in the "PCI Express stack", composed of three Layers.

1. The physical layer.
2. The data link layer.
3. The transaction layer.

Packets are transmitted serially at very high speeds, so a series of decoding, sequence recovery, and CRC checks are required. But we don't have to worry about such a complicated thing, there's something called "PCI Express stack" that handles them, including the physical layer, the data link layer, and the transaction layer. (If you don't know how to translate it, call it a business layer.)

The first and layers is the ones implemented for us in the PCI Express FPGAs core (usually a combination of hard and soft CORE) and handling all the complexity. As a user, we work on the transaction layer, where life was easy, the sky was blue and girls is beautiful.

The first two layers are given to the FPGA core to achieve, as a user, we only need to care about the transaction layer, where life is wishful, the sky blue, green grass, beauty everywhere ~ (haha, see here laugh Aloud)

In more details:

1. The physical layer:that ' s where the pins is toggling. The 8b/10b encoding/decoding and the lanes disassembly/reassembly is done there.
2. The data link Layer:that ' s where data integrity is checked (CRCS) and packets are re-transmitted if required (hopefully a Rare occurance).
3. The transaction layer:that ' s the user level. Once A packet arrives here, it's guaranteed to be good data.

Good data? That's great, that's what we want!

Let's see how working in the transaction layer looks like.

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PCI Express (iii)-A story of packets, stack and network