ZED-Board from entry to master series (7) -- Vivado + SDK for MP3 playback

This article describes how to develop a PS bare metal application on the Qaq platform through Vivado IDE. By comparing with this series of blogs (3), readers will see that Vivado development is more efficient and fast.

 

We have heard of MP3. Now we can use ZED-Board to listen. The audio chip ADAU1761 is available on the board for recording and playing, but not MP3 decoding. Q dual-core arm9-do MP3 software decoding should be possible, but the blogger himself has a VS1003 which can implement MP3 hardware decoding and the software will be simplified, if you are interested in the MP3 decoding principle, You can thoroughly study how to use CortexA9 + ADAU1761 for MP3 playback. The circuit diagram is as follows:

 

Use Zynq MIO to implement VS1003 control, which is only related to PS, and PL can be discarded completely. Based on this section, you can try to move the SPI module to PL to reduce the I/O read/write frequency of the PS part and improve the CPU utilization. The physical connection diagram is as follows:

Zynq board external with a mother, in order to use the dubang line, you need a dual public needle, can be pressed with a single row 54mm needle

The following describes the software development process. Create a Vivado project named MP3Player. The procedure is as follows.

 

After entering IDE, click Create Block Design under IPI Integrator in the left-side Process Manager. This tool is available only after version 2013.1. It will replace XPS for system integration.

Right-click the editing area and select Add IP.... The default name is "design_1.bd ".

Enter Qaq in the search box, double-click the first one, and add the IP address to the circuit diagram.

After adding the Block, the system automatically performs cabling and runs Block Automation in the circle area.

Wait for completion. The result is shown in.

As you can see, DDR and fixed IO are automatically connected. This is because we chose ZedBoard DVK when creating the project, so that we can automatically connect the pins to the corresponding peripherals according to the board description.

In addition, M_AXI_GP0 is enabled by default. You can connect the IP address of the PL part with the AXI interface to the PS for control. This section is not required, so it must be disabled. Otherwise, an error will be reported during design verification. Double-click the square, see

You can see familiar and unfamiliar pictures, some of which are like the semi Q view in XPS, but they are much simpler. Click PS-PL Configuration on the left. The page is as follows:

Deselect the check box after the AXI GP0 interface, confirm, and return to IPI.

Verify the Design. Right-click the blank area and click Validate Design. No error. Click OK.

Click Generate Block Design at the position to confirm.

In the Sources window, right-click design_1 and choose generate top-level HDL package. Confirm.

Click Generate Bitstream in the left-side flow, one step in place. It takes about 5 ~ to complete the bit stream ~ 8 min.

After that, Open Implementated Design and export it to the SDK.

 

After that, Open Implementated Design and export it to the SDK. If you do not perform this step, the second item will become gray.

The SDK is developed later, which is the same in this series (3. Create an Application project, a C project, and a template helloworld. Change the code to the following:

# Include <stdio. h> # include "platform. h "# define MIO_BASE 0xE000A000 # define DATA00x40 # define DATA0_RO 0x60 # define DIRM_00x204 # define includelay (unsigned int t) {unsigned int I, j; for (j = 0; j <t; j ++) {for (I = 0; I <600; I ++) ;}/ * functions * // * MAIN function *//*--------------------------------------------- Required */# define partition (MIO_BASE + DATA0, 12) # define partition (MIO_BASE + DATA0, 12) # define VS_DREQ DrvGPIO_GetBit (MIO_BASE + DATA0_RO, 11) # define compute (MIO_BASE + DATA0, 10) # define VS_XDCS_1DrvGPIO_SetBit (MIO_BASE + DATA0, 10) # define compute (MIO_BASE + DATA0, 13) IO_SetBit (MIO_BASE + DATA0, 13) # define partition (MIO_BASE + DATA0, 0) # define partition (MIO_BASE + DATA0, 0) # define partition (MIO_BASE + DATA0, 9) # define struct (MIO_BASE + DATA0, 9) void DrvGPIO_ClrBit (volatile unsigned int * p, int idx); void DrvGPIO_SetBit (volatile unsigned int * p, int idx ); unsigned char DrvGPIO_GetBit (volatile unsigned int * p, Int idx); void init_vs1003 (void); void VS_Reset (void); // VS1003 soft reset and initialization void VS_Write_Reg (unsigned char addr, unsigned char hdat, unsigned char ldat ); // write an unsigned int VS_Read_Reg (unsigned char addr) to the function register of VS1003; // read a word void VS_Send_Dat (unsigned char dat) from the function register of VS1003 ); // send the audio data void VS_Flush_Buffer (void) to VS1003; // clear the data buffer void VS_sin_test (unsigned char x) of VS1003; // sine test void LoadPatch (void ); // For VS1003 Patch void SPI_WriteByte (unsigned char x); # include "mp3.h" void print (char * str); int main () {init_platform (); print ("Hello World \ n \ r"); unsigned int I; init_vs1003 (); VS_Reset (); // VS1003 reset initialize VS_sin_test (200); // sine test, you can hear VS_Flush_Buffer (); for (I = 0; I <sizeof (mp3_table); I ++) {VS_Send_Dat (mp3_table [I]);} while (1) {DrvGPIO_ClrBit (MIO_BASE + DATA0, 7); delay (40000); DrvGPIO_SetBit (MIO_BASE + DATA0, 7); delay (4000 0);} return 0;} void DrvGPIO_ClrBit (volatile unsigned int * p, int idx) {(* p) & = ~ (1 <idx);} void DrvGPIO_SetBit (volatile unsigned int * p, int idx) {(* p) | = (1 <idx );} unsigned char DrvGPIO_GetBit (volatile unsigned int * p, int idx) {return (* p) & (1 <idx)> idx);} void init_vs1003 (void) {second (MIO_BASE + OEN_0, 7); DrvGPIO_SetBit (MIO_BASE + DIRM_0, 7); Second (MIO_BASE + OEN_0, 0); Second (MIO_BASE + DIRM_0, 0 ); drvGPIO_SetBit (MIO_BASE + OEN_0, 9); DrvGPIO_SetBit (MIO_BASE + DIRM_0, 9); Second (MIO_BASE + OEN_0, 10); Second (MIO_BASE + DIRM_0, 10); Second (MIO_BASE + OEN_0, 12); Second (MIO_BASE + DIRM_0, 12); DrvGPIO_SetBit (MIO_BASE + OEN_0, 13); DrvGPIO_SetBit (MIO_BASE + DIRM_0, 13);} void SPI_WriteByte (unsigned char x) {unsigned char I = 0; for (I = 0; I <8; I ++) {if (x & 0x80) {SPI_MOSI_1;} else {SPI_MOSI_0;} SPI_SCL_0; SPI_SCL_1; x <= 1 ;}}/*************************** ***************************************- Function Description: write Data (one word, two bytes) to the function register of VS1003-subordinate module: VS1003B module-function attribute: external, user-callable-parameter description: addr is the address of the function register. hdat is the high-byte ldat to be written. ldat is the low-byte to be written.-Return description: no response ************************************** * **************************/void VS_Write_Reg (unsigned char addr, unsigned char hdat, unsigned char ldat) {while (! VS_DREQ); // VS_XCS_0 is received only when VS1003 DREQ is high. // enable slice selection and SCI is valid. In this way, the function register can be read and written to SPI_WriteByte (0x02 ); // write operation code 0x02 00000010 (function register write operation) SPI_WriteByte (addr); // write Register address SPI_WriteByte (hdat); // write high-byte SPI_WriteByte (ldat ); // write the low-byte VS_XCS_1; // close the slice selection, invalid SCI }/************************************ * *****************************-function description: VS1003 soft reset and initialization (set clock frequency and volume)-subordinate module: VS1003B module-function attribute: external, user callable-parameter description: None-return description: no ******************* **************************************** * ******/Void VS_Reset (void) {VS_XRESET_1; delay (100); VS_XRESET_0; delay (100); VS_XRESET_1; // hardware reset, XRESET effective low-level delay (100 ); VS_Write_Reg (0x0804x04); // software reset, write 0 x SM_SDINEW to register 0 as 1 SM_RESET as 1VS_Write_Reg (0x03,0x98,0x00 ); // set the clock, write 0x9800 SC _MULT to register 3 to set 4 SC _ADD to 3 SC _FREQ to 0VS_Write_Reg (0x0b, 0 x, 0x00); // set the volume, the maximum volume of both left and right channels is VS_XDCS_0; // enable data slice selection. Note that XCS (chip selection) is high, and SDI valid SPI _ WriteByte (0); // write data. Four zeros are written here, which are irrelevant data and used to start data transmission. SPI_WriteByte (0); SPI_WriteByte (0); SPI_WriteByte (0 ); VS_XDCS_1; // disable data slice selection, invalid SDI }/************************************ * *****************************-function description: write a byte of audio data (that is, the data used for playback) to VS1003. Note: Set VS_XDCS to 0 before calling the function. Select the data chip-subordinate module: VS1003B module-function attribute: externally, you can call-parameter description: dat is the byte to be written-return description: no *************************************** * **************************/void VS_Send_Dat (unsigne D char dat) {VS_XDCS_0; // enable SDI. You can write audio data to VS1003 while (! VS_DREQ); // VS1003 DREQ is high to write data SPI_WriteByte (dat); // VS_XDCS_1 writes a byte of audio data to VS1003 through SPI; // disable SDI }/********************************** * *******************************-function description: write 2048 zeros to VS1003 to clear the VS1003 data buffer. Note: Call this function to clear the VS1003 data buffer after a complete audio (such as a complete MP3) is played, prepare the following audio data (MP3. -Subordinate module: VS1003B module-function attribute: external, user-callable-parameter description: None-return description: no *************************************** * *************************/void VS_Flush_Buffer (void) {unsigned int I; VS_XDCS_0; // enable data slice selection, that is, enable SDI transmission for (I = 0; I <2048; I ++) {VS_Send_Dat (0 );} VS_XDCS_1; // disable data slice selection }/******************************** * **********************************-function description: sine test. This is an effective way to test if the VS1003 chip is normal !! -Subordinate module: VS1003B module-function attribute: external, user can call-parameter description: x determines the frequency of the sine wave generated in the sine test, the frequency that directly affects the voice.-Return description: no *************************************** * *************************/void VS_sin_test (unsigned char x) {VS_Write_Reg (0x0820x20); // start the test and write 0 x SM_SDINEW to register 0 as 1 SM_TEST as 1 while (! VS_DREQ); // wait until DREQ changes to high VS_XDCS_0; // select SDI effective SPI_WriteByte (0x53) when opening the data disk; // write the following 8 bytes, enter the sine test SPI_WriteByte (0xef); SPI_WriteByte (0x6e); SPI_WriteByte (x); // The parameter x is used to adjust the frequency of the sine wave in the sine test. FsIdx (b7 ~ B5): index S (b4 ~ B0): sine wave hop frequency F = Fs x s/128SPI_WriteByte (0); // For example, x = 126 (0b 011 11110) fsIdx = 011 = 3 Fs = 22050Hz S = 11110 = 30 F = 22050Hz X 30/128 = 5168 HzSPI_WriteByte (0); SPI_WriteByte (0); SPI_WriteByte (0 ); delay (6000); // delay for a period of time, in order to hear the "positive chord" SPI_WriteByte (0x45); // write the following 8 bytes, exit sine test SPI_WriteByte (0x78); SPI_WriteByte (0x69); SPI_WriteByte (0x74); SPI_WriteByte (0); SPI_WriteByte (0); SPI_WriteByte (0 ); SPI_WriteByte (0); VS_XDCS_1; // disable data slice selection. SDI is invalid}

 

Audio files need to be converted to C header files, which can be implemented using matlab:

clear;clc;close all;f = fopen('222.mp3','rb');a = fread(f,'uint8');fclose(f);fb = fopen('D:\Tutor_My\MP3Player\MP3Player.sdk\SDK\SDK_Export\mp3\src\mp3.h','w');fprintf(fb,'const unsigned char mp3_table[] = {\r\n');fprintf(fb,'0x%02x,\r\n',a(1:end));fprintf(fb,'\r\n};');fclose(fb);

Download and run the bitstream. You can use headphones to hear the mp3 you have converted.

 

It takes 10 minutes to complete the above project. The operation is completely completed by Vivado + SDK, and the operation is very simple and concentrated.