FPGA Image Processing-pip

FPGA Image Processing-pip

Introduction to the hardware structure and software:

FPGA, arria ii gx series chip. Altera Development Board, http://www.altera.com.cn/products/devkits/altera/kit-aiigx-pcie.htmlmy Development Kit information.

Two important information: FPGA: EP2AGX125EF35. DDR2: 1G, 64-bit. It runs at 200 MB.

The input value is 1080 P, that is, 1920*1080. Each of the 8 bits in RGB format has a total of 24 bits. The clock speed is 148.5 MB. Output is also 1080 P. That is, DDR2 transmits data at a rate of P.

I Mao Hua Wang QQ849886241, my blog http://blog.csdn.net/my_share

This is.

The big image is 1080 p, and the small image is 1/16 p of p. People are me. Haha. Ugly.

 

Problems and Thoughts in the process of completion

We need to store the big image and small graph data in ddr2. How can we save the data to achieve that effect ???

The size of the thumbnail, 480*270. The position is 50 points above, 200 points on the right, and 1240 points on the left.

Method 1:

Save the entire large image, and set the pixels of the big image to the corresponding DDR2 address, from the 0--1920*1080 position to the corresponding pixel position .. Then, the ddr2 bucket at the position where the thumbnail is displayed is overwritten with the color of the thumbnail, the first line of the figure ddr2 address is about 50*1920 + 1240 to 50*1920 + 1720. One row overwrites 270 rows.

Then read the ddr2 address one by one, and the result is displayed.

Method 2:

It is to read all pixels of the big image to the ddr2 address from 1---1920*1080, and then read the small image to the ddr2 address from 2000*1080. What about next? When the big image is input to the position of the small image, that is, when the field frequency VS to 50, HS to 1240, the first point of the small image is read from ddr2, overwrite the pixel value of the big image. This is the input time yo, VS, HS is the big picture. Then overwrite the data of the big image (the input is the big image ). That is, one-to-one coverage. In fact, the first method is to cover the DDR2 position of the big image when the small image comes over. Now, before entering ddr2 in the big image, we will use the data of the previous small image to overwrite it, and then read it into ddr2.

Method 3:

In the preceding example, all pixels in the big image are read to the ddr2 address from 1---1920*1080, and then the small image is read to the ddr2 address from 2000*1080. What about next? When reading, when the scene frequency VS to 50, HS to 1240, the first point of the small figure is read from ddr2. This field frequency and line frequency are the line frequency field frequency read to the display, and the second method is the line frequency field frequency read from the big picture. That is to say, the area is covered by a thumbnail when it is read to the display.

Here I just briefly explain my solution. In the ddr2 section, I didn't specify how to read it, how much data to read at a time, how to configure RAM and fifo to work with ddr2 storage.

In fact, the first method is not feasible, because a small image overwrites a large image or a large image overwrites a small image ?? Because I currently use a single camera. If there are two cameras, the coverage time will be faulty. If you are not sure who will cover the image, the image will flash, that is, a large image will be a small image. Therefore, the first solution is not desirable. I didn't use the second method either. Although it could be completely covered, there was no problem, but there were also a lot of problems. The thumbnail was saved in ddr2 before, and then covered the big image, it seems that the thumbnail is a frame late, but it cannot be seen. In fact, the problem is complicated, and the small graph also needs to be updated in real time, and then it needs to be read together to cover the big image and stored in. There is no third solution, and the implementation is simple (in fact, it is not much worse ). So I used the third solution.

 

When I describe the hardware and ddr2, I will consider whether the ddr2 throughput is sufficient. Add a small graph to P. In this case, the throughput is sufficient. However, at the time of writing, I did not care at all, resulting in a lack of throughput. So I would like to remind you that at present, according to the efficiency of the dd2 controller I use, a small figure is added to the 1080p, throughput approaching ddr2 continues.

 

If you do the same, let's take a look.

 

Q: When fpga is used for image processing (for example, the image is stored in SDRAM, but I want to extract it for parallel processing. How can this problem be achieved?

Read-> process-> write
Generally, the read speed is faster than the algorithm core, or the number of digits read is greater than the number of digits processed (128 bits read in a single cycle, and the operation is 32 bits). This gives FPGA the possibility of parallel processing.

Introduction to fpga Digital Image Processing

I learned about icdesign on the FPGA platform. I usually hope that I can enter the icdesign company after graduation. Using FPGA as a product alone has little market space. It is very difficult to develop a website on your own.
If you do not want to take a postgraduate entrance exam after graduation, we suggest you try to enter the icdesign company. However, there will be a lack of practical experience to make up. Video Compression (encoding and decoding) is a good direction, but it is difficult to keep up with the pace of technological development by self-study alone. H.265 will be promulgated this year, and AVS 2.0 in China will be promulgated soon. Hardware Implementation of these algorithms is very difficult.
Other aspects of digital image processing, such as the branches related to display, may not be mastered by self-study alone.
Sorry, I said a bunch of difficulties. But the direction should be positive.