FPGA learning notes Altera FPGA using JIC file to configure the Cure tutorial (GO)

Many of the friends who have done microcontroller know that after the MCU is burned to write the program firmware, then the program firmware is stored inside the MCU. The program can continue to operate even if the MCU is powered off and then re-energized. This is because the firmware of the MCU is written to write the program firmware to the MCU on-chip program memory ROM, and most modern MCU this ROM is flash memory. Flash memory can be power-down to keep data, so can realize the power-down program is not lost. Altera or Xilinx FPGA chips use SRAM-based lookup tables, and one of the big features of SRAM is that power-down data is lost, When we use JTAG to configure the SRAM configuration file (. sof) into the FPGA chip, the data is stored directly in the SRAM structure of the lookup table, so once the chip power down, the data in the SRAM will be lost, again after power, SRAM will no longer have valid data. This is what we common, when using JTAG to download the SOF firmware into the FPGA, the board re-power, the previous download of the firmware is not the reason. When our system is stable and mass produced, of course, we want to be able to permanently maintain the circuit firmware, that is, the FPGA after power on its lookup table is written to valid data. But we can't always use JTAG to download the program firmware every time the system is power up. Therefore, the FPGA supports a different configuration: active serial configuration.

The so-called active serial configuration, is to put a piece of FPGA chip to be able to lose the power of the data is not lost memory, such as the most common EPCs, qflash, parallel flash, to store the design of the circuit firmware. In the FPGA chip, a dedicated hardware circuit is designed to read the firmware stored in the memory at the moment the chip has just been power-up, and it is configured in every SRAM of the FPGA chip. In such a way, without changing the FPGA chip SRAM process of the look-up table structure, so that every time the chip on the power, can obtain effective configuration data. External storage Circuit configuration information for the chip, which we call the configuration chip. In previous years, Altera's FPGA chip indicated that only using its own EPCS chip as an external configuration device, the EPCs chip is essentially an SPI interface serial flash chip, but has been rigorously tested by Altera, excellent performance. In recent years, with the continuous development of chip production technology, many other manufacturers of SPI interface Flash chip can also reach EPCS technical standards, so Altera released the limit, and pointed out that other chip manufacturers can use the SPI interface Flash chip instead of EPCs. Our core Route starter Board on the use of a piece of St company production of 16Mbit serial flash chip m25p16 to be used as a configuration chip. The chip has excellent performance and is fully capable of achieving EPCS performance standards, while the cost is less than half of the EPCs chip with the same capacity.

When we need to solidify the design of the configuration firmware into the device, there are two ways, the first way, that is, the traditional way is to use a dedicated as interface (independent of the JTAG 10-pin interface) to directly write the configuration chip, which requires a separate as interface on the circuit board, occupy the PCB area. The second way, and now the popular way is through the JTAG interface, through the FPGA chip indirectly burning the configuration chip. Our Development Board does not have an independent as interface, so it only supports the second type of write. The following is a practical example of how this type of burning is explained.

1, open the hope of curing FPGA design project, here I directly open the button to shake this lesson of the project.

2, in Quartus II software, click File->convert Programming Files, as shown in:

3, in the pop-up window, programming file type selects Jtag Indirect Configuration file (. jic), Mode selects active serial,configuration Device selection Epcs16,file name default is Output_file.jic, here, we develop a good habit, change it to project name: Key_filter.jic.

4, in the input files to convert column, click on the Flash loader, click on the Add Device option on the right, as shown in: (Warm tip: Click on the image to see the large HD image)

5, click on the Add Device option in the pop-up tab, select Ep4ce10, then click OK, as shown: (Warm tip: Click on the image to see the big picture)

6, click OK will return to the previous configuration page, the mouse click on the SOF Data again, then click on the right side of the add File, as shown: (Warm tip: Click on the image to see the big picture)

7, in the pop-up window, found in the Output Files folder "Key_filter.sof" file, click Open, you can add it, as shown: (Warm tip: Click on the image to see the large HD image)

8, click on the open, go back to the Configuration page, click on the Generate button, as shown: (Warm tip: Click on the image to see the large HD image)

9, after clicking the Generate button, then the software starts to convert the file, after the successful conversion pop-up Prompt window, as shown: (Warm tip: Click on the image to see the big picture)

10, click OK, then close window.

11, open the Download tool in Quartus II programmer, move the original SOF file out, re-add Key_filter.jic file in, tick programming/configuration, As shown: (Warm tip: Click on the image to see the big picture)

12, after the setup is complete, click Start (if the download and Development Board is properly connected), then the software starts to burn the firmware, the whole burning time is about 20 seconds. After the burn is complete, the firmware is saved in the configuration chip, but at this point the FPGA is not able to run the firmware, because the current firmware is present in the configuration chip, and is not configured in the FPGA, it is necessary to have the FPGA to perform an active configuration of the firmware from the configuration chip process, the method is simple, Power off the development board after it has been powered off. At this point, we press the key 0 or the key 1, you can see the status of the LED has changed. Power off the power, the firmware is still maintained, the entire design curing work completed.

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FPGA Learning notes Altera FPGA uses the JIC file to configure the Cure tutorial (GO)