a single operation of the MIPS CPU can load or store 1 to 8 bytes of data. The multiplication result registers are interlocked (interlocked) Because the result of the multiplication is not enough to allow the next instruction to automatically get the result. Attempting to read the result register before the multiplication operation completes causes the CPU to stop running until it is complete. One of the goals of the MIPS architecture, compared to some of the simpler RISC architectures, is that the architecture is moving toward a four-bit development, making the segment structure of an address unnecessary. (This burden is also in the X86 kernel PowerPC )
Functional Groupings:
null operation:NOP,ssnop(cannot be launched simultaneously with other instructions, at least one clock cycle required)
data transfer directives between registers:move,movf,movt,movn,Movz(after four for conditional delivery instructions)
constant Load directives:dla,la(macro instructions to get some label address or variable address in the program);dli,li(load constant immediate number instruction);lui (Load high-order immediate number instructions)
arithmetic / logic operation instructions:Addu、Addiu、Daddu，Daddiu(addition instruction);dsub、Sub(The subtraction operation that triggers the overflow);Dsubu、Subu(General subtraction instruction);ABS、Dabs(for absolute operation);Dneg、neg、Dnegu、Negu(Unary non-operational); and、Andi、or、Ori、XOR、Xori、nor、 not(bitwise logical instructions);Drol、Dror、Rol、Ror(cyclic left and right shift);DSLL、Dsll32、DSLLV（ -Bit left shift, low 0);Dsra、Dsra32、Dsrav（ -Bitwise arithmetic Right SHIFT command);DSRL、Dsrl32、Dsrlv（ -Bitwise logical RIGHT SHIFT command);SLL、SLLV（ +Bit left shift command);SRA、Srav（ +Bitwise arithmetic Right SHIFT command);srl、Srlv（ +Bitwise logical RIGHT SHIFT command);SLT、Slti、Sltiu、Sltu(Hardware instruction, condition satisfied on write1, otherwise write0）；seq、SGe、Sgeu、Sgt、Sgtu、SLE、Slue、SNe(Macro instructions for setting the destination register based on more complex conditions)
integer multiplication, division, and redundancy instructions:Ddiv、Ddivu、Div、Divu(Integer division of3Operand macros are handled separately -Bit or +Bit signed or unsigned number);Divo、Divou(It is clear that the instruction is a division instruction with overflow checking);Dmul、Mul（3Number of operands -Bit or +Bit multiplication instruction, no overflow check);Mulo、Mulou、Dmulo、Dumlou(Multiplication macro instruction, if the result can not be stored in a general register, overflow, triggering exception);Dmult、Dmultu、mult、Multu(Execute a signed/No sign32/64-bit multiplication of machine instructions);Drem、Dremu、REM、Remu(Redundancy operation);Mfhi、Mflo、Mthi、Mtlo(Used to access the result register of an integer multiplication cellHiAndLo）
Access instruction (Memory access instruction):lb、LBU(Load a byte, the high can be 0, or symbol expansion to complement the length of the entire register);LD(Load a double word);LDL、Ldr、LWL、LWR、SDL、SDR、SWL、SWR(left, right load, store one word, double word);LH、Lhu(Loading a half word, high can be 0, or symbol expansion to supplement the length of the whole register);LW、LWU(Load a word);pref、Prefx(The data is pre-buffered);SB、SD、SH、SW(Storage byte, double word, half word, word);Uld、Ulh、Ulhu、ULW、USD、USW、Ush (Address non-aligned data Access macro directives)；L.D、L.s、S.D、S.S(Access to double and single-precision floating point number of instructions, address must be aligned);ldxcl、lwxcl、sdxcl、swxcl(with base Address register+The address of the offset register access instruction);
jump, Branch, and subroutine invocation directives:J(Unconditionally jump to an absolute address, access256MCode space);JAL、JALR(direct or indirect subroutine invocation, this jump can not only jump to the specified address, but also the return address (the current instruction address+8) put inRARegister);b(Unconditional relative jump based on the current instruction address);Bal(function call instruction based on the current address);bc0f、bc0f1、bc0t、bc0t1、bc2f、bc2f1、bc2t、bc2t1(depending on the co-processor0And2The conditional sign to jump);bc1f、bc1f1、bc1t、bc1t1(Jump based on the floating-point condition flag);beq、beq1、BEQZ、BEQZ1、BGE、Bge1、Bgeu、BGEU1、Bgez、BGEZ1、BGT、BGT1、Bgtu、BGTU1、BGTZ、BGTZ1、ble、Ble1、Bleu、BLEU1、Blez、BLEZ1、BLT、BLT1、Bltu、BLTU1、Bltz、BLTZ1、bne、Bnel、Bnez、Bnezl(Double-operand and single-operand comparison jump instruction);bgeza1、Bgeza11、bltza1、Bltza11(If you need , these instructions are the original machine instructions for the conditional function call);
Breakpoints and trap directives: Break(Produces an exception of type "Breakpoint");SDBBP(GenerateEJTAGException breakpoint instruction);Syscall(produces a convention for the type of exception used by the system call);Teq、Teqi、Tge、Tgei、TGEIU、Tgeu、TLT、Tlti、Tltiu、Tltu、Tne、Tnei(Conditional exception instruction, a condition test for one or two operands);
coprocessor 0 Features: Span style= "Font-family:times New Roman;" >CFC0 , ctc0 (copy data into and out of coprocessor 0 Control register); mfc0 , mtc0 , dmfc0 , dmtc0 (in general Register and Coprocessor 0 exchange data between registers); , ctc2 , dmfc2 , dmtc2 , mfc2 , (coprocessor 2 instructions); Compilation Data Summary: Http://www.cnblogs.com/kingwolfofsky/archive/2011/09/02/2163457.html
Go MIPS instruction Set
