Go: Intel CPU address Space Summary

One, address space mapping

Here is the Intel architecture of the CPU address space layout, note that there is no memory address space layout.

We say that memory is usually referred to as Dram,dram relative to the CPU can also be an external device, the CPU address space is the CPU access to external devices in the process of a concept, the CPU in addition to access to the DRAM will also access many other devices. The CPU address space can be roughly assumed to contain the DRAM address space, but the two are different concepts. And the DRAM address space is accessed directly by the memory controller and accessed indirectly by the CPU.

For a long time the Intel CPU was 32 bits, that is, the address space can be accessed to 4GB, but the dram is usually between 512MB to 2GB, now assuming that the DRAM is 1GB, then the 3GB address space is empty. Inside the computer, the address is also a resource. This empty address space is used to access external device IO, which is called Mmio (Memory Mapped I/O). The Mmio space is large, it contains the PCI configuration space (256MB or larger), built-in integrated memory (256MB, or larger), and many other things. So the size of this part cannot be ignored.

Now the Intel CPU is generally 64-bit, that is, can access to 64GB. And the DRAM is getting bigger, so that DRAM plus mmio space beyond 4GB, and mmio space is not arbitrarily changed. So now the way to do is to re-map part of the DRAM to more than 4GB of space, the following is a dram 5GB as a case, do an example. Please look

In the left is the address space, the right is the DRAM space, where the red font represents the register, you can find the description of the register in the spec, these registers determine the entire address space of the large pattern. Here is a brief description.

Tolud, point to the 32-bit address, which is within 4GB. It is a dividing line between 0-tolud and DRAM,TOLUD-4GB for Mmio space. This value is specified by the BIOS. For illustrative purposes, assume that the tolud is specified as 2GB.

Tom, it's not clear at the moment, I guess it means the actual physical memory size, "the total amount of populated physical memory", such as Tom 5GB. BDFR (0,0,0,A0) can be verified on this machine.

Remapbase and Remaplimit, also 36-bit, represent base and upper address respectively. Used to remap part of the space in DRAM that is obscured by Mmio, 2GB. The diagram maps the partially obscured parts of the DRAM to Tom, so Remapbase is 5gb,remaplimit to 7gb-1.

touud,36 bit address, the size of remaplimit+1 location, such as Touud should be in the position of 7GB, can be compared with tolud to understand, Tolud is 4GB within the dividing line of DRAM and Mmio, Touud can be understood as the dividing line between DRAM and Mmio in 4GB-64GB.

The above is assuming that the DRAM exceeds 4GB, if the DRAM is only 3GB, and Tolud is specified as 2GB? That is, 2GB-3GB's dram is obscured. It is also redirected to the top of 4GB by Remapbase and Remaplimit. And assuming that DRAM is only 2gb,tolud 2GB? There is no remapping at this time. Remaplimit is less than remapbase (typically remaplimit is 0), which means no remapping is used.

For more than 4GB of how the space is accessed, please check the page description:

Http://en.wikipedia.org/wiki/Physical_Address_Extension

Second, address space layout

The layout of the address space below 4GB is highlighted here. Here is the layout of my Visio drawing, in fact, the layout described in the spec is all integrated into a picture, which is the core of the previous period summed up.

In the same picture, the red font is part of the register, which is closely related to the layout of the address space. A detailed description of these registers can be found in spec. For example, "egress Port registers" This 4KB window, will be placed according to the Epbar settings of any DMI interface location Mmio, but so that the window can not overlap with any other windows.

In addition, I will explain what I have learned.

1. First look at the location of TOLUD-4GB, you can see that there are several places are DMI Interface (subtractive Decode). DMI is the South Bridge and North Bridge interface, access to DMI, that is, access to the South Bridge.

In addition to explain is substactive decode, in the computer address decoding has three forms, when the main device through the specified address to access the bus from the device, one is positive decode, has been decoded from the device to access their own, so it will respond, Otherwise, there is no response from the device, one is negative decode, from the device received the address decoded after the discovery does not belong to their own address range, from the device is forwarded out; one is subtractive decode, no response from the device in 4 clock cycles, The address is sent to the extended bus to decode.

　　　　　　　　　　　　

Citation: http://www.microsoft.com/whdc/system/bus/pci/default.mspx

DMI Interface (subtractive Decode) means that the CPU sends an address first to the North Bridge decoding, if the address does not occupy the North Bridge device, then the address will be transmitted to the South Bridge decoding, that is, access to the South Bridge device. It can be assumed that the first 4GB space is the DMI Interface (subtractive Decode), and then 0-tolud by the Dram Declaration of occupation, TOLUD-4GB is also occupied by a variety of devices, so left a fragmented number of DMI Interface. (At the moment it seems that this understanding is fluent, but I hope it is also correct).

2. Explain the high BIOS again. The BIOS firmware address is divided into three segments, the high BIOS here, the system BIOS behind it, and the extended system BIOS behind it. As already stated in spec, the command executed at the start of the computer starts in the high BIOS. However, the high bios in the 4GB position, the computer reset after the entry is real mode. Intel architecture next to the beginning of the address of the hidden high portion of all 1, so although the logical address of the first instruction is f000:fff0, but the physical address of the access is FFFF_FFF0, this address is less than 4G 16 bytes, so the BIOS is generally placed only a jump instruction here, Far jump or near jump, in the EFI BIOS, it is through a near-jump transfer bios without entering the real mode, directly set up a descriptor, and finally into flat mode (belongs to the protection mode). The key is that the address space is programmable between 640KB-1MB (PAM0-PAM6), which can be specified as read-only, write-only, read-write, and disable, all for DRAM. After booting this space is disabled, and DRAM is North Bridge equipment, disable DRAM, then this address space is sent to the South Bridge to decode (against the above for DMI interface explanation to explain), the result is decoded to the high BIOS corresponding firmware. So the instructions are still executed in the high BIOS.

You can use RW to verify that the PAM0 (PCI 0/0/0 90H) Bit[5:4] is set to 00, then it is found that the data between 0F0000-0FFFFF and Ffff_0000-ffff_ffff is the same. It is also proved that in the case of DRAM disabling, the two-part addresses are decoded to the same place.

If PAM0 is set to read-only or read-write, the information on the DRAM is read, and the data content is the system Bios. Why does the system BIOS actually run into DRAM in the firmware? Shadow, only the North Bridge in charge of the address decode, the address to the ROM instead of the ROM inside the data copy into the DRAM inside. This is a conceptual problem. In fact, the BIOS is usually done when the data in the ROM is copied to the low-end memory, (0~640k) in one or two segments, and then extract the data into the corresponding segment. such as e000,f000 and so on. And then turn off the whole map. When the address is decode, it corresponds to the actual DRAM rather than the ROM.

3. Then talk about the PCI configuration space. can see its base address is determined by Pciexbar, with the RW software to verify that the PCI data can be seen in memory. The address space for each PCI can be calculated using this formula: PCI Express Base address + Bus number x 1 MB +device number x KB + Function number x4 KB. For example, in My computer's pciexbar see the base address is f400_0000, when I want to access the bus (0) device (1F) function (3), by the calculation can be obtained by f40f_b000, and then from the PCI 0/1f/ The data you see in 3 is the same as the data you see from the f40f_b000 location of the memory. Note that the bit0 of Pciexbar is set to 1 when viewed.

Pciexbar-pci Express Register Range Base Address
B/d/f/type:0/0/0/pci
Address offset:60-67h
Default value:00000000e0000000h
Access:ro, r/w/l, r/w/l/k
Size:64 bits

4. To illustrate probably this, the role of the other various address windows, address space location, can be easily found in spec. In addition, the relevant registers of each interval are also indicated in the figure.

Original link:

Http://www.biosren.com/viewthread.php?tid=3200&extra=&ordertype=1&page=1

Go: Intel CPU address Space Summary