(go) Tell me about chip design.

Chip design This business, from the big aspect, mainly divided into analog and digital two chunks, and each large and sub-front and back end, I think most of the students on this is definitely very clear, the following on the digital circuit chat chip design Some things, is the chip design has what to do, this is not a complete system introduction, Just a personal understanding and summary, I hope, may not be comprehensive, not correct, welcome students to correct and add to the digital chip, can not say FPGA, this is a programmable digital circuit, the use of the principle is not said, the goal of digital circuit design, is to make these features, made our own dedicated ASIC/SOC , so that no matter the area, cost or security, etc. can be guaranteed. In terms of process, the approximate steps of digital chip design are system and function definition, RTL implementation, verification, synthesis and testability design (synthesize, DFT), ATPG simulation, timing analysis, to Automatic layout (APR). To the GDS network table of the Fab. This process can be iterative, and there may be differences in the approach and implementation process for each of the different types of chips, such as the pure number ASIC or hybrid circuit (mix-signal) and the system-level chip (SOC). Here are some of the main issues that are discussed in detail in these basic processes.

The main design of the system design to function definition and architecture design, configuration of bus architecture, module design, data flow distribution, clock design and other issues. The bus includes a number of factors such as between modules, between the module and the MCU core, or between the external host and the chip, or test needs. Clocks involve the planning of data streams, communication interfaces or internal MCU clock conventions, process conditions, power dissipation and other factors. Modules require explicit interfaces and definitions. In the system-level design, especially in many digital-analog hybrid circuits or in the power consumption of special requirements of the circuit, but also the design of the voltage domain, between different modules, functional modules and interfaces may need to be based on the process conditions, power consumption requirements set different voltages. Whether the clock, or voltage, can be achieved through the control switch to achieve the power consumption requirements, clock implementation is relatively simple, in most circuits can achieve this clock control, voltage control is generally implemented in the integrated power management chip on the larger chip. But the future trend is that even without a power management chip, the voltage gating needs to be taken into account.

In SOC system design, an important link is the MCU core selection, now commonly used core is arm, older ARM7, ARM9 and other series, newer is the three series Cortex A, R, M, the specific use does not do detailed NFPs, selected after the core needs to be set, The general hardware does not need to know too much about its instruction set, but need to understand its bus interface, data bus, instruction bus, and storage system design, generally need to arrange ROM, ram as instruction and data memory, because ROM is not changed, It is also common to add flash as a patch to write to. External memory or DMA controller may also be required to increase external storage space. The allocation of the address is done according to the function needs, there are now many tools such as Synopsys designkits can generate external bus code and address assignment.

The first step to complete the system and function definition, it is necessary to implement the RTL implementation, RTL is specifically describing the hardware circuit of the tool language, there are Verilog and VHDL, RTL characteristic is the hardware on the trigger, different from the software in order to execute, the circuit has the timing logic and composition logic, The timing logic is in the physical form of registers, which are controlled by the clock, which represents the data or control signals in the circuit that are driven by the clock. The combinational logic is a circuit block which is not controlled by the clock, and the combinational logic, as its name implies, generates some logical results directly through the combination of some signals.

RTL design, a big problem is the asynchronous design problem, asynchronous data processing according to different situations there are many ways, the simplest, if the asynchronous level signal, can be directly in the new clock domain with 2 level register to isolate, to avoid metastable occurrence. For the bus processing, or pulse processing, it is necessary to synchronize the module, the synchronous mode is generally referred to the need for handshake signal, is the previous level clock to tell the sampling clock, the signal OK, sampling the second clock to pick up, and then tell the previous level of the clock, I got it, so the previous level of clock can be changed data or other processing One situation is that the previous level clock is too fast, causing the second stage too late, you need to add FIFO as isolation, is to let those data first put, I am slowly to take. This FIFO design involves read and write address judgment, write full or read empty need to do the corresponding processing, read and write address between the judgment can only be in one of the clock domain, which itself involves the processing of asynchronous signal, which is generally solved with Grema, or some places directly can judge the address high, The purpose of these methods is not to allow the address to be unstable at the time of comparison.

The design of the clock itself in the RTL design problem should also be noted that we in a chip, as far as possible to put the clock generation circuit in a piece, mainly from a comprehensive, DFT perspective to consider, let these clocks unified management and constraints. The frequency of the clock, switching also to special treatment, otherwise prone to burr and other things. There are many issues to be aware of in RTL design, such as comprehensiveness, and the need to take into account the area of the circuit, as well as the response speed, which are the fundamental problems of RTL coding.

After the code has been written, it is necessary to do the verification work, the following talk about this matter.

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Last time after writing, there is support, there is a friend said that the meaning of writing these things, if on some of the details of interested friends can explore and learn from each other, can also communicate privately this is just my point of view to write these things, I hope you correct and add. Next to the day before, continue the verification section.

Chip verification generally have these aspects, one is RTL or netlist (pre or post PR with SDF), this is the general sense of the chip verification work, one is FPGA-level, also RTL, but download to the FPGA, with the help of hardware environment, can also To do application experiments directly.

The workload of chip verification occupies most of the time and effort in chip design, whether it is that kind of verification, it is necessary to set up a test platform (testbench), to verify that the platform simulates the working environment of the chip from the software structure. There is a clear connection structure, as well as the non-structural functions or task packages required to complete these tests. Test platform in the test chip is RTL, test vectors or the applied excitation can be VERILOG/VHDL,HDL language itself has a relatively perfect behavior-level description function, but also to meet the vast majority of test platform construction and testing incentives, of course, we face more complex design, Or the pursuit of more efficient can also use other compiler-compatible languages, such as C + +, SC, sv,e and so on.

It is clear that test incentives are time-based, and that the use of these non-circuit description languages and functions and software is almost indistinguishable, so there are a number of techniques for using the software, such as object-oriented programming techniques, SystemVerilog, Specman, in order to enter and drain the chip sequentially. E, SV also support assertion statement (assertion), different manufacturers provide OVM, VMM,UVM, etc. also includes a lot of class library to use. In fact, these technologies can be explored in more depth, but also look forward to the interests of further development. Whether traditional validation or the latest validation methodology, it is necessary to pursue the convergence of verification, that is, verification is completely automated detection, unless the debug, we do not have to pass the waveform to determine whether the test pass or not. For many verification, we almost do not need to go to the FPGA verification, such as data communication classes, can be fully software to achieve data generation and comparison. While some applications, such as video, graphics capture, and so on, if you enter the FPGA can realize the performance of the test, the FPGA process here does not make a statement, but note that we use as a stream of the RTL code may differ from the code to be burned into the FPGA, For example, some of the IP used in the FPGA may be different from the flow film manufacturers, there are some ports and so need to pay special attention.

There is also post layout of post-imitation, which refers to the DfT and APR after the network table, with timing information to join the SDF file for simulation. Some people say that I have done verification, between the code and the Web table, PR before and after the network table consistency between the validation has done, but also need to imitate it? The answer, of course, is still needed because consistency does not detect many timing problems, such as glitches, even DFT errors, functional problems, and so on.

Now more common digital-analog hybrid chip verification, the simulation of the part is mainly used Verilogams modeling, of course, there are vhdlrn modeling and so on, these things are introduced to control and detectable analog, into the digital simulation system, is also a link to the digital verification process. More professional digital-to-analog hybrid verification system ADMS, which introduced a number and simulation of multiple engines, such as digital nc_verilog analog Eldo and so on, the digital part of the RTL code, the simulation part of the direct import of the GDS circuit, of course, in order to speed up, the simulation part in use generally still imported digital model.

Soc verification, embedded in the burning ROM software, in the simulation verification system, the use of the general memory model plus text format code files, the general implementation is directly through the system read-in instructions to read the file into the memory model. (Some simulation tools can be imported directly through the option, like SDF files, such as tool NSCIM), the emulator can directly write the command execution log for debug, but there is now a more advanced way for complex SOC verification, such as Codelink tools, can be based on the original emulator, Establish the relationship between MCU and HDL circuit software, and make debug easier by displaying the link of waveform and firmware (firmware) source code. The following need to say that the implementation of the part, is integrated, DFT, STA, ATPG, etc., ready to write together, interested friends can go on my writing, I do not do this update, I hope friends play a relay.

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The topic of the post received attention, was also refined, encouraged, has been wanting to continue to write, but the time is limited, more mainly inertia by the end, has not been finished, today to be well-off, continue to talk about the digital IC design next some of the work. But before I go on, what I'm saying is, actually, I just thought And then knocked down, not complete, especially now the chip design, different products, the requirements are different, the design of the steps are not exactly the same. For example, many design digital circuits may implement a software model to evaluate our frequency, resources, or signal-to-noise ratios in digital signals processing, and these are some of the things that need to be done before the design of the specification.
After the chip has completed the design and verification, we have to do is to install it into a GDS grid, is called the implementation (Circuit implementation), which includes the process of synthesis, DFT, formality, STA, ATPG pattern generation and simulation (as well as functional verification including pre-and post-imitation), and then into the back-end of the PR/LVS/DRC process, this is a physical design, of course, this process is general, here is mainly about several back-end physical design before the front-end implementation of several steps.
The integrated principle is more intuitive, from RTL to Gtech Library to the factory process library compiled translation mapping and substitution, the integration needs to input is the clock constraint is the SDC file, SDC is the design and product use requirements of the decision.
DFT consists of several types, scan chain is the most common one, this can be done together in a comprehensive step, can also be carried out after the synthesis, the number of scan chain and the size of the chip itself and the chip can provide a test chip pin, as far as possible to scan the chain of the length of the shorter the better, to shorten the test time Because some films have a limited pin, need to compress the scanning chain, and even some chips because the reusable pin too little, into the test mode is required in the function mode by the host settings, set and then exit the function mode. Scan chain can be generated by the tool ATPG pattern, DFT success depends on the test coverage, generally in more than 95% of the description is almost OK, if the coverage is low, need to investigate the reasons, generally see if there is no missing DFF, and why will slip away, the general reason is not this, Is that some uncontrolled nodes cause low coverage and need to do some processing in the circuit to make the relevant ATPG produce, such as the optional DFF or level/ground that are added to the test mode.
Some circuits include the rom/ram, you need to add the Rom/ram itself to the built-in self-test circuit (BIST), generally if the SOC with the MCU, you can actually complete the RAM test through the software, not necessarily add BIST, but the embedded CPU software Rom must have a bist circuit to complete the self-test, the principle of self-test circuit is very simple, is to determine whether the data written and read the match, otherwise the Bist circuit will give the wrong identification.
Boundary scan chain is another DFT, and it's easy to understand that we can control the input and output values of each pad on the chip, so it can be applied to board-level debugging.
Formaliry or Equence check, the main check synthesis, DFT and back-end PR and before the respective steps of the rtl/grid equivalence.
STA is a static timing analysis, mainly used after the chip to complete the back-end process, but also check whether the timing requirements, especially after inserting the clock tree, which requires the back-end tool (Icc/encounter, etc.) anti-marked SDF file for analysis. The details are not table. After the STA is finished, it can perform post-imitation and Atpg pattern after function.

Reference documents:

[1] Original address: http://bbs.eetop.cn/thread-340177-1-1.html

(go) Tell me about chip design.