Go The problem of non-aligned access under MIPS

1. Questions

When reading or writing to a data unit using a fetch instruction under MIPS, the destination address must be an integer multiple of the number of bytes of data being accessed, which is called address alignment.

For example, on the MIPS platform, when LH reads a half word, the memory address must be an integer multiple of 2; when LW reads a word, the address of the memory must be an integer multiple of 4; When the SD writes a double word, the memory address must be an integer multiple of 8. If the destination address is not aligned at the time of the visit, it will cause an exception, typically after the system prompts "bus error" to kill the process directly.

See a test program (godson 2E Platform):

#include <stdio.h>
#include <sys/sysmips.h>

unsigned short data[] = {
0x1, 0x2, 0x3, 0x4,
0X55AA, 0X66BB, 0x77cc, 0x0000,
};

inline void unaligned_access (unsigned short * const row)
{
ASM volatile
(
". Set mips3\n\t"
". Set noreorder\n\t"

"LWR $1 (% 1) \n\t"
"Lwl $11, 4 (% 1) \n\t"
"or $, $11\n\t"
"LD $2 (% 1) \n\t"/*%1 is a double word aligned,%1+2 is double word unaligned */
"SD $ $,%0\n\t"

". Set reorder\n\t"
". Set mips0\n\t"
: "=m" (* (ROW))
: "R" (row+4)
: "$8", "$9", "$"
);
}

int main ()
{
printf ("---------------------------------------------------------\ n");
printf ("Testing Godson2 unaligned access instruction \ n");
printf ("---------------------------------------------------------\ n");

Sysmips (mips_fixade, 0);

Unaligned_access (data);

printf ("Result is:0x%04x%04x%04x%04x\n", data[3], data[2], data[1], data[0]);

}

After the program runs, the system prompts "illegal instructions" and exits.


CISC (such as x86), if the destination address is not aligned, the CPU does not fall into an exception because there is a micro program that handles non-aligned access inside it.


2. Resolve

In high-level languages, this is generally not a problem, and compilers often handle the alignment of data types. But what if I encounter it, or if I meet it in the assembly, I can't avoid it?

The LWR/LWL, SWR/SRL, LDR/LDL, sdr/sdl command pairs available in the instruction set of MIPS can be used. Their principle can be used to make a simple signal (take LDR/LDL for example, other similar):





Explained in the case of small-end mode, the case of the big-endian mode is the opposite: first LDL t0, 0 (T1), then Ldr t0, 7 (T1).

can see regardless of the big-endian mode or the small-end mode, non-aligned access to the resolution of the original Instruction (aligned access) is done in two steps, that is, first take the beginning address addr to the next alignment address of the part of the data, placed in the right side of the register (small end), (big-endian placed in the left ( Then take some data from the alignment address to addr + len-1 (len is the length of the data unit, the half word is 2, the double word is 8), and place the left part of the register (small end).

such as the small end machine, the starting address is T1 = 0x1022, then:

Ldr t0, 0 (T1) take 0x1022~0x1027 to the right of T0
LDL t0, 7 (T1) take 0x1028~0x1029 to the left of T0

Note that the suffix R (right) of the above instruction, L (left) is relative to the register, the load operation is to take the part of the data, placed in the register to leave or right, the store operation is to register the data in the left or left part, write to the destination address. The format of both the big and small end registers is fixed, i.e. the right end is low and the left side is high. Any first LDR/LDL/LWR/LWL/SDR/SDL/SWR/SWL can only access the initial address of the memory to the next alignment address.

Go The problem of non-aligned access under MIPS