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The I2C (Inter-Integrated Circuit) bus is a two-line serial bus developed by Philips to connect the microcontroller and its peripheral devices. The I2C bus was originally developed for audio and video devices in 1980s and is now mainly used in server management, including communication in the status of a single component. For example, the administrator can query each component to manage system configurations or master the functional status of the component, such as power supply and system fan. Multiple parameters such as memory, hard disk, network, and system temperature can be monitored at any time, which increases system security and facilitates management.
1 I2C bus features
The main advantage of I2C bus is its simplicity and effectiveness. Because the interface is directly on the component, the space occupied by the I2C bus is very small, which reduces the space of the circuit board and the number of chip pins, and reduces the interconnection cost. The bus can be up to 25 feet in length and support 40 components at a maximum transmission rate of 10 Kbps. Another advantage of the I2C bus is that it supports multimastering, in which any device capable of sending and receiving can become the master bus. A master can control signal transmission and clock frequency. Of course, there can only be one master at any time point.
2 bus composition and signal type
The I2C bus is a serial bus consisting of the SDA data line and the clock SCL, which can send and receive data. Two-way transmission is performed between the CPU and the Controlled IC, and between the IC and IC. The maximum transmission rate is 100 kbps. Various controlled Circuits are connected in parallel on this bus, but just like telephones, only dialing their respective numbers can work. Therefore, each circuit and module has a unique address, in the process of information transmission, each module circuit connected to the I2C bus is both the master controller (or controller) and the transmitter (or receiver), depending on the functions it wants to accomplish.
The control signal sent by the CPU is divided into address code and control amount. The address code is used for site selection, that is, the circuit to be controlled is connected to determine the type of control; the control value determines the type (such as contrast and brightness) of the adjustment and the amount to be adjusted. In this way, although each control circuit is mounted on the same bus, it is independent of each other and irrelevant to each other.
The I2C bus has three types of signals during data transmission: start signal, end signal, and response signal.
Start signal: in high-power mode, SDA switches from high level to low level to start transmitting data.
End signal: in high-power mode, SDA changes from low-level to high-level and ends data transmission.
Response signal: After receiving 8-bit data, the IC that receives the data sends a specific low-level pulse to the IC that sends the data, indicating that the data has been received. After the CPU sends a signal to the controlled unit, it waits for the controlled unit to send a response signal. After the CPU receives the response signal, it determines whether to continue to transmit the signal based on the actual situation. If no response signal is received, it is determined that the controlled unit has a fault.
At present, many semiconductor integrated circuits have integrated I2C interfaces. Single-Chip Microcomputer with I2C interfaces include: cygnal's c8051f0xx series, philipsp87lpc7xx series, and microchip's pic16c6xx series. Many peripheral devices, such as memory and monitoring chips, also provide I2C interfaces.
In the process of I2C bus communication, the types of information transmitted between the two parties involved in the communication are summarized as follows.
The main controller sends the following types of information to the Controller: start signal, stop signal, 7-bit address code, read/write control bit, 10-bit address code, Data byte, restart signal, response signal, clock pulse.
The controller sends the following types of information to the master controller: Response signal, Data byte, and low clock level.
This section analyzes the status and timing of several signals that may occur during I2C bus communication.
① The bus is idle.
The SDA and SCL signal lines of the I2C bus are in the idle state at the same time. At this time, the output-level FET of each device is in the cut-off state, that is, the bus is released, and the two signal lines pull up each other to Increase the level.
② Start signal.
The SDA level of the data line is lowered (that is, the negative hop) during the high-level period of the clock line SCL, which is defined as the start signal of the I2C bus, it marks the beginning of a data transfer.
The start signal is a time series signal of Level Jump, rather than a level signal. The start signal is automatically Established by the master controller. Before the signal is established, the I2C bus must be idle, as shown in figure 1.
③ Stop the signal.
During the High-level period of the clock line SCL, the SDA of the data line is released, so that the SDA returns a high-level (positive jump), known as the I2C bus stop signal, marking the termination of a data transmission.
The stop signal is also a time series of Level Jump, rather than a level signal. The stop signal is also established by the master controller. After the signal is established, the I2C bus returns idle status.
④ Data bit transfer.
Each bit of data transmitted on the I2C bus has a corresponding clock pulse (or synchronous control), that is, with the combination of the SCL serial clock, each bit of data is serialized on SDA.
During data transmission, the SDA level must be stable during the high-level period of the SCL. The low level is DATA 0, and the high level is data 1.
The SDA level change status is allowed only when the SCL is low. The level of logical 0 is low, while the level of logical 1 depends on the positive Supply Voltage VDD of the device itself (when using an independent power supply), as shown in 2.
⑤ Response signal.
All data on the I2C bus is transmitted in 8 bytes. Each byte sent by the transmitter releases the data line during the time pulse 9, and the receiver returns a response signal.
When the response signal is low, it is specified as a valid response bit (ACK), indicating that the receiver has successfully received this byte. When the response signal is high, it is specified as a non-response bit (NACK). Generally, it indicates that the receiver failed to receive this byte.
The requirement for feedback of the effective response bit Ack is that the receiver lowers the SDA line during the low level before the 9th clock pulses, and ensure that the clock is stable during the high-level period.
If the receiver is the master controller, after it receives the last byte, it sends an Nack signal to notify the controlled transmitter to end data transmission and release the SDA line, so that the master receiver sends a stop signal P, As shown in 3.
⑥ Insert wait time.
If the controller needs to delay the time when the next Data byte starts to be transferred, the controller can wait by powering down and holding the clock line (SCL.
Once the Controller releases the clock line, data transmission continues, giving the Controller enough time to transfer the received data bytes or prepare the data bytes to be sent.
After the Controller with CPU responds to the received address byte, it takes some time to execute the interrupt service subroutine to analyze or compare the address code, in the meantime, we will place the SCL Wire Clamp on the low power level, and release the SCL line after proper processing, so that the master controller can continue sending subsequent data bytes, as shown in figure 4.
7. Restart the signal.
After a data communication (send or receive) is completed during the master control bus, if you want to continue to use the bus for another Data Communication (send or receive) without releasing the bus, it is necessary to re-start the SR signal timing.
The restart signal Sr is the end of the previous data transmission and the start of the next data transmission. The advantage of the restart signal is that the master controller does not need to release the bus between the two communications, so that the control of the bus is not lost, that is, other master device nodes are not allowed to seize the bus.
⑧ Clock synchronization.
If two master device nodes exist in an I2C bus system, they are respectively recorded as master device 1 and master device 2, and their clock output ends are clk1 and cl [0, they all have the ability to control the bus.
Assume that in a certain period, the two have successively sent different clock pulse sequences clk1 and clk2 to the SCL line (the High and Low Frequency widths of the clock pulse are regularly generated by their internal dedicated counters), this can happen before the control of the bus is determined.
In view of the "line and" characteristics of the I2C bus, the clock signal waveform obtained on the clock line SCL is neither as expected by the main device 1 clk1, it is not like the clk2 expected by the master device 2, but the logic and result of the two.
The waveform of clki and clk2 is used as the common synchronous clock signal. Once the control of the bus is determined to a master device, the bus clock signal is generated only by the master device, as shown in Figure 5.
⑨ Bus conflict and bus arbitration.
Assume that there are two master device nodes in an I2C bus system, which are respectively recorded as master device 1 and master device 2, and their data output ends are data1 and data2, both of which have the ability to control the bus, there is a possibility of a bus conflict (that is, a write conflict.
Assume that the two initiate signals to the bus one after another. In view of the "line and" feature of I2C bus, the signal waveform obtained on the data line SDA is the result of the two phases of data1 and data2, the descent edge of data1 is treated as the descent edge of SDA.
After the bus is started, master device 1 attempts to send data "101 ......", Master device 2 attempts to send data "100101 ......".
Each time the two main devices send a data bit, they must perform sampling on the signal level at their output end. As long as the sampling result is consistent with their expected level, they will continue to occupy the bus, the control of the bus cannot be determined.
The 3rd-bit active device 1 is expected to send "1", that is, to send a high level within 3rd clock cycles.
During the High-level period of the clock cycle, when the main device 1 Performs routine sampling, it is detected that an unmatched level is "0". At this time, the main device 1 has to give up the bus control scheme; therefore, the master device 2 becomes the only master of the bus, and the control of the bus finally gets the ruling result, thus realizing the function of bus arbitration.
From the completion process of the above bus arbitration, we can conclude that no data is lost during the arbitration process between the master device 1 and the master device 2. Each master device has no priority, and the control of the bus is randomly determined, even the master device 1, which first sends the startup signal, is not controlled yet.
In fact, the system follows the arbitration principle of "low-level priority". It judges the bus to the master device that sends low-level data lines first, and other master devices that send high-level data lines will lose control of the bus, 6.
⑩ Bus blocking status.
In special circumstances, blocking or disabling the bus is a feasible way to disable all communication activities on the I2C bus, as long as any device attached to the bus locks the clock-line SCL to the low-power flat.
Go to: IIC Time Series
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