How to Write makefile files in Linux

Article Title: How to Write makefile files in Linux. Linux is a technology channel of the IT lab in China. Includes basic categories such as desktop applications, Linux system management, kernel research, embedded systems, and open source.

Compilation and link of Programs

----------

Here, I would like to talk about some of the program compilation Specifications and methods. Generally, whether it is C, C ++, or pas, you must first compile the source file into an intermediate code file, in Windows, that is. obj file, which is in UNIX format. o File, that is, Object File. This action is called compile ). Then merge a large number of Object files into the execution File. This action is called link ).

During compilation, the compiler requires correct syntax and correct declaration of functions and variables. For the latter, you usually need to tell the compiler where the header file is located (the header file should only be declared, and the definition should be placed in the C/C ++ file), as long as all the syntax is correct, the compiler can compile the intermediate target file. In general, each source file should correspond to an intermediate target file (O file or OBJ file ).

The links are mainly linked functions and global variables. Therefore, we can use these intermediate target files (O files or OBJ files) to link our applications. The linker does not care about the source File where the function is located, but only about the intermediate target File of the function. In most cases, due to too many source files, too many intermediate target files are generated during compilation, during the link, you need to clearly specify the intermediate target file name, which is inconvenient for compilation. Therefore, we need to pack the intermediate target file, in Windows, this package is called "Library File", that is. lib File. In UNIX, it is an Archive File, that is. file.

To sum up, the source file will first generate the intermediate target file, and then the intermediate target file will generate the execution file. During compilation, the compiler only checks program syntax, and whether functions and variables are declared. If the function is not declared, the compiler will give a warning, but the Object File can be generated. When linking a program, the Linker will find the function implementation in all Object files. If it cannot be found, it will report the Link Error code (Linker Error). In VC, this error is generally caused by a Link 2001 error, which means that the linker cannot find the function implementation. You need to specify the Object File of the function.

Well, let's get down to the truth. GNU make has a lot of content, so we can start with it.

Makefile Introduction

-------

When executing the make command, you need a Makefile file to tell the make command how to compile and link the program.

First, we use an example to describe the writing rules of Makefile. In order to give everyone a sense. This example is from the GNU make user manual. In this example, our project contains 8 C files and 3 header files, we need to write a Makefile to tell the make command how to compile and link these files. Our rules are:

1) if this project has not been compiled, all our C files must be compiled and linked.

2) if several C files of this project are modified, We will compile only the modified C files and link them to the target program.

3) if the header file of this project has been changed, we need to compile the C files that reference these header files and link them to the target program.

As long as our Makefile is well written, we can use only one make command to complete all this, the make command automatically and intelligently determines which files need to be re-compiled based on the current file modification, so as to compile the required files and link the target program.

I. Makefile rules

Before talking about this Makefile, let's take a rough look at the Makefile rules.

Target...: prerequisites...

Command

...

...

Target is a target File, which can be an Object File or an execution File. It can also be a Label. For the Label feature, it will be described in the subsequent "pseudo-target" chapter.

Prerequisites is the file or target required to generate the target.

Command is the command to be executed by make. (Any Shell command)

This is the dependency of a file. That is to say, one or more target files depend on the files in prerequisites, and their generation rules are defined in command. To put it bluntly, if more than one prerequisites file is newer than the target file, the command defined by command will be executed. This is the Makefile rule. That is, the core content in Makefile.

In the end, Makefile is like this, as if my document should be over. Haha. This is the main line and core of Makefile, but it is not enough to write a Makefile. I will give you some experience in the future. There are plenty of contents. :)

Ii. Example

As mentioned above, if a project has three header files and eight C files, we want to complete the three rules described above, our Makefile should look like the following.

Edit: main. o kbd. o command. o display. o \

Insert. o search. o files. o utils. o

Cc-o edit main. o kbd. o command. o display. o \

Insert. o search. o files. o utils. o

Main. o: main. c defs. h

Cc-c main. c

Kbd. o: kbd. c defs. h command. h

Cc-c kbd. c

Command. o: command. c defs. h command. h

Cc-c command. c

Display. o: display. c defs. h buffer. h

Cc-c display. c

Insert. o: insert. c defs. h buffer. h

Cc-c insert. c

Search. o: search. c defs. h buffer. h

Cc-c search. c

Files. o: files. c defs. h buffer. h command. h

Cc-c files. c

Utils. o: utils. c defs. h

Cc-c utils. c

Clean:

Rm edit main. o kbd. o command. o display. o \

Insert. o search. o files. o utils. o

The backslash (\) indicates a line break. This makes it easier to read Makefile. We can save this content in a file named "Makefile" or "makefile", and then directly enter the command "make" in this directory to generate the execution file edit. If you want to delete the execution file and all the intermediate target files, simply execute "make clean.

In this makefile, the target file contains the execution file edit and intermediate target file (*. o), the dependent files (prerequisites) are the ones after the colon. c file and. h file. Each. o file has a set of dependent files, and these. o files are dependent files of the execution file edit. The dependency essentially describes the files generated by the target file, in other words, the files updated by the target file.

After the dependency is defined, the subsequent line defines how to generate the operating system commands for the target file, which must start with a Tab key. Remember, make does not care about how the command works. It only executes the defined command. Make will compare the modification date of the targets file and the prerequisites file. If the date of the prerequisites file is newer than the date of the targets file, or the target does not exist, then, make will execute subsequent defined commands.

It should be noted that clean is not a file, it is just an action name, a bit like lable in C language, and there is nothing after the colon, so, make will not automatically find the dependency of the file, and will not automatically execute the subsequent commands. To execute the subsequent command, you must clearly name the lable after the make command. This method is very useful. We can define unnecessary compilation or compilation-independent commands in a makefile, such as program packaging, program backup, and so on.

3. How does make work?

By default, we only enter the make command. So,

1. make will find the file named "Makefile" or "makefile" in the current directory.

2. If it is found, it will find the first target file (target) in the file. In the above example, it will find the file "edit, and use this file as the final target file.

3. If the edit file does not exist or is later than the edit file. o if the file modification time of the file is newer than that of the edit file, the file will be generated by executing the command defined later.

4. If. o file also exists, so make will find the target in the current file. o file dependency. If found, it will be generated based on that rule. o file. (This is a bit like a stack process)

5. Of course, your C files and H files exist, so make will generate. o file, and then use. o The ultimate task of file life make, that is, execution file edit.

This is the dependency of the entire make. make will find the dependency of the file layer after layer until the first target file is finally compiled. In the process of searching, if an error occurs, for example, if the dependent file cannot be found, make will exit directly and report an error. For the defined command error, or the compilation fails. make does not care. Make only depends on the file dependency, that is, if the file after the colon is still not found after I find the dependency, I am sorry, I will not work.

Through the above analysis, we know that such commands as clean are not directly or indirectly associated with the first target file, and the commands defined after it will not be automatically executed. However, we can show that you want to execute make. That is, the command -- "make clean" to clear all target files for re-compilation.

So in our programming, if this project has been compiled, when we modify one of the source files, such as file. c. Then, based on our dependencies, our target file. o will be re-compiled (that is, the command defined after this dependency), so file. o files are also up-to-date, so file. the file modification time of o is newer than that of edit, so edit will be relinked (For details, refer to the Command defined after the target file of edit ).

If we change "command. h", kdb. o, command. o, and files. o will be recompiled, and edit will be relinked.

[1] [2] Next page