In embedded development, delayed function calls are often encountered. For example, Data Interaction conflicts between nodes must be considered during protocol preparation. The time consumed by each instruction execution on 51 series single-chip microcomputer is known, so the precise delay is easy to implement. In the series processor, the execution of commands adopts the pipeline technology, and the machine cycle parsed by the compiler is unknown in terms of application layer programming. Therefore, it is difficult to implement precise latency. In general applications, timers are often used to solve such problems. Besides the timer module, there is also a periodic interval timer module in the ARM7 processor. Periodic interval timers generally provide time interval interruptions for the scheduling program of the operating system. The PIT design provides the precision of program time management. The schematic diagram shows the periodic interval timer. PIT has a programmable overflow counter, which has the feature of automatic reset after overflow. PIT is based on two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. The clock of both Counters is 1/16 of the master clock. After the PITIEN bit of the PIT_MR mode register is set to interrupt enabling, The CPIV counter starts counting from 0 until the overflow value defined by the PIV field of the mode register PIT_MR. After the CPIV counter overflows, it is immediately reset to 0, while the PICNT register accumulates. The PITS of the Status Register PIT_SR is set to trigger the interruption. After the CPIV and PICNT values are obtained by reading the periodic interval value register PIT_PIVR, the overflow counter (PICNT) is reset and PITS is cleared to confirm the interruption. The periodic interval timer interrupt mode continues. The enable and disable of the periodic interval timer are implemented by the PITEN bit of the register PIT_MR. Note that the PITEN operation is valid only when CPIV is 0. The following describes how to use the periodic interval timer module to generate a scheduled interrupt function. [Html] www.2cto. comvoid ClockHandler (void) _ irq {Display_Received ++; * Signature = * AT91C_PITC_PIVR; // Acknowledge Interrupt void PIT_Init (void) {* Signature = signature | AT91C_PITC_PITEN | 784741; <span style = "white-space: pre"> </span> // configure AT91F_AIC_ConfigureIt (AT91C_BASE_AIC, AT91C_ID_SYS, 1, scheduled, (void (*) () ClockHandler); // trigger method of Interrupt and function entry address AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_SYS); // Enable Interrupt}