Linux kernel patch AMD bypass translation buffer (TLB) error

AMD's bypass switching buffer (TLB) error and its impact on Quad-core Haolong chips have been reported last week. according to foreign media reports, AMD is running a 64-bit RedHat Enterprise Edition Linux, that is, Upgrad.

There have been many reports on AMD's bypass switching buffer (TLB) error and its impact on Quad-core Haolong chips last week. according to foreign media reports, AMD is preparing a kernel patch for 64-bit Red Hat Enterprise Edition Linux, namely Upgrade 4. Unlike AMD's BIOS (Basic Input/Output System) repair and microcode update, it is reported that these processes have reduced the performance by 10-20%. it is said that Linux patches consume less than 1% of the performance. However, we also learned that users must sign a confidentiality agreement to obtain the patch.

Once confirmed, AMD published the source code for the patch on the x86-64.org mailing list. However, the code is based on the status quo and does not need to be modified. it is warned again that it is not fully applicable to mainstream systems:

This patch has powerful intrusion features and has a very small number of affected users (if some of your systems are affected, you will understand this ), we do not recommend using this patch on conventional Linux systems. This patch is not prepared for mainstream users, nor is it used for sales of Linux products! This patch has only undergone minimum functional tests. Each user must evaluate it before use to ensure that it complies with the necessary quality standards.

In a previous article on the same mailing list, AMD employee Elsie Wahlig also warned that the patch "not recommended for upstream products ". Wahlig mentioned that the patch was developed by AMD's operating system research center team for Linux 2.6.23.8 and provides a detailed error description:

Error 298 is described as follows: "The processor operation may not be atomic. in the second-level cache, change the Accessed or dirty bytes from 0b to 1b addresses in the page Conversion Table project. During a small interval, before the modified copy data returns to the second-level cache, other cache operations may cause invalid page conversion table items to be installed in the third-level cache. In addition, if the cache row is detected during this interval, the processor will not cache the Accessed or dirty bytes or data that may be incorrect. The system may report a level-3 Cache Protocol error through a machine detection event. In this case, the content of the MC4 status register (MSR 1__0410) will be B2000000_000B0C0F or BA000000_000B0C0F. The content of the MC4 address register (MSR 2017_0412) will be 26 h. "

Wahlig describes how the Linux patch works. the patch bypasses the BIOS workspace and simulates "accessed and dirty bytes" to prevent incorrect data from creating a file header:

The kernel patch solution depends on the root cause of the second-level cache export problem. The problem is exposed only when TLB needs to set A or D bit in A page table Project. If TLB never needs to set an A or D bit, the error will not occur. By simulating the and D bits using the current writable bits, the patch ensures that the actual A and D bits are often preset. When you access A page that does not set simulation A bit for the first time, and when you write A page that does not set simulation D bit for the first time, this process is completed by forcing an error page. Simulation A and D-bit storage in-place registers, the operating system can usually obtain it in the page table Project.

AMD, in a more euphemistic statement than originally expected, stops releasing the patch, but the company does not issue a "pass" to all Linux users to avoid performance loss caused by BIOS fixes.