PCIE_DMA instance One: xapp1052 Detailed usage instructions

A: Preface

A lot of me as a beginner. PCIe hardware engineers will encounter such a problem, see a lot of PCIe-related information, or can't figure out how to use this thing. So we turned on the Core_generator tool on the ISE, generated a PCIe IP core, emulated the example design with Modelsim, and analyzed it as if the protocol part was understood more deeply. As for how to use, hehe ...

Of course, most hardware engineers are self-motivated! So we went online to find information, found a Xilinx official produced demo:xapp1052. Full name is bus Master DMA performance demonstration Reference Design for the Xilinx Endpoint PCI express®solutions. Tall on Ah, finally know where to use, decisive download down. Open a look, a lot of things, according to the inside Xapp1052.pdf instructions, step by step to generate bit, download to the Development Board, and then install the host computer software, and finally test and use chipscope to grasp the signal analysis. But in fact, you are so stupid that you can't even generate a bit (friends who meet the same situation please silently praise me). Just when you anxious, you see this great blog .... Next, I will teach you how to use this xapp1052.

Second: Pre-preparation

1, the PCIe Foundation is still to have, especially the agreement part. Recommend an ebook, very classic, please read it patiently (Addison.wesley.pci.express.system.architecture.ebook-lib.chm): http://download.csdn.net/ download/yuzeren48/7723815

2, a Development Board, I use the Xilinx ML605.

3. A host with PCIe slots.

4, Xapp1052 Demo (http://download.csdn.net/download/yuzeren48/7723795)

5. ISE14.1 Kit

Three: Instructions for use

1, open coregenerator generate a 4 channel Gen2 PCIe IP Core, configuration section see, pay particular attention to Classcode must be ' h058000, otherwise unable to install the driver normally. Except for a few changes in the diagram, the rest are the default settings

Figure 1 Configuration 1

Figure2 config 2

Figure 3 Configuration 3

Figure 4 Configuration 4

Figure 5 PCIe Core Directory

2, establish Bmd_dsign project. Complete Engineering Document (http://download.csdn.net/download/yuzeren48/7723831). Download needs points, we recommend you follow the instructions step by step to establish themselves. First open Ise, new project, add file. File from:

.. \v6_pcie_v1_7\source All

.. XILINX_PCIE_2_0_EP_V6_04_LANE_GEN2_XC6VLX240T-FF1156-1_ML605.UCF and Xilinx_pcie_2_0 in the \v6_pcie_v1_7\example_design _ep_v6.v

.. \xapp1052\dma_performance_demo\fpga\bmd\common All

.. BMD_64_RX_ENGINE.V and BMD_64_TX_ENGINE.V and V6_PCI_EXP_64B_APP.V in \xapp1052\dma_performance_demo\fpga\bmd

Then compile, because you want to compile BMD_PCIE_20.V first, so right-click Manual Compile order,6 shown.

Figure 6 Compiling the project

Select All. V and. UCF files, complete the synthesis and layout cabling, and generate a bit file, shown in 7.

Figure 7 Generating a bit file

Note: If you feel that this compilation is not comfortable, you can not see the hierarchy structure. You can delete the bmd_pcie_20.v and remove the ' ifdef pcie2_0 from all the files.

3, Modelsim Simulation

Many people feel that directly write bit to the Development Board, with Chipscope online debugging can. Small series think it is best to use Modelsim to do a simulation, to determine the logic no problem and then burn the board. Small series had several times burned the wrong bit, with chipscope how can not catch the signal. Next we'll talk about how to simulate.

The first thing to do is. The files under the \v6_pcie_v1_7\example_design folder (except for xilinx_pcie_2_0_ep_v6.v) are all deleted and will be: All the files under \dma_performance_demo\fpga\bmd\common and. \dma_performance_demo\fpga\bmd under BMD_64_RX_ENGINE.V and BMD_64_TX_ENGINE.V and V6_PCI_EXP_64B_APP.V copied to: The \v6_pcie_v1_7\example_design folder.

Then modify: \v6_pcie_v1_7\simulation\functional under the BOARD.F file, note that BMD_PCIE_20.V must be placed at the top of the compilation, as shown in the modified BOARD.F file 8:

Figure 8 The modified BOARD.F

Finally, open the Modelsim se10.1b software and change the directory to. . \v6_pcie_v1_7\simulation\functional

Input script do simulate_mti.do simulation results 9 shown in Figure 10

Figure 9 Simulation Results 1

Figure 10 Simulation Results 2

Note: The Modelsim simulation here does not use the DMA function, just to test our code integrity. If you need to simulate the DMA function, you can call the function in PCI_EXP_USRAPP_TX.V, write the address, length and so on in the DMA control register, and then start the DMA read or write.

4, chipscopes grasping packet analysis

First, you need to add the Chipscope core in the ISE project, chipscope the use of the method described in (http://download.csdn.net/download/yuzeren48/7705033), This gives the ISE project file with the Chipscope core (http://download.csdn.net/download/yuzeren48/7723831)

After the CDC is inserted, the bit is generated, downloaded to the board, the board is plugged into the PCIe slot of the host, and the Power Device Manager detects a PCI memory controller. Use the steps in Xapp1052.pdf to force the installation of the driver. After installing the drive, open software 11 shown

Figure 11 Host computer software

Test Write First:

The pattern to write is changed to 0x01020304, and the rest remains the default setting. Click Start, in the chipscope we can see that the DMA control register received a total of multiple packets from the host, 12 (note, set Windows to 8,depth 8, and set the trigger signal 13).

Figure 12 Host write DMA control register

Figure 13 Setting the trigger signal

These packages are used to write the DMA control registers, and these packages are presented in the following order:

When the host writes 0x00000001 to a register that has an offset address of 04, the DMA initiates write memory mode, as shown in 14. (We can detect the DMA write start by setting the low 32 bits of the trigger signal trn_rd to 0x01000000)

Figure The DMA write memory

The same method, test read. We can read the memory through DMA. 15 is shown

Figure DMA Read memory