Physical Address Extension (PAE) paging mechanism

Intel increases the number of pins on the processor from 32 to 36 to improve the addressing capability of the processor to 2 ^ 3664 GB. Therefore, a new paging mechanism needs to be introduced. 64 gb ram is divided into 2 ^ 24 page boxes. the physical address field of the page table item is extended from 20 to 24. each page table item must be...

Intel increases the number of pins on the processor from 32 to 36 to improve the addressing capability of the processor to 2 ^ 36 = 64 GB. therefore, A new paging mechanism needs to be introduced.

 

64 gb ram is divided into 2 ^ 24 page boxes. the physical address field of the page table item is extended from 20 to 24. each page table item must contain 12 flag bits (fixed) and 24 Physical

Address bit (36-12), a total of 36 bits, therefore, each page table item must be extended from 32 bits to 64 bits (36 bits> 32 bits, considering alignment, therefore, the page table item should be doubled to 64 bits ).

 

In the case of 4 KB regular paging, because each page table item is 64, the original 210 page table can only contain 512 table items, which occupies 32

9 digits in a linear address. Similarly, because the page Directory items have the same structure as the page table items, the higher-level page directory tables can only contain 512 page table items.

The number of digits remaining in a 32-bit linear address is: 32-bit (total number of digits)-12-bit (intra-page offset)-9 (index in the page table) -9 digits

(Index in the page directory table) = 2 bits. at the same time, Linux introduces a new page table level of a page directory index table (PDPT), which consists of four 64-bit table items and remains

To point to one of the four items in PDPT.

 

The following four figures describe the structure of the page table in four cases (derived from Wikipedia)

 

The 4 K paging page structure of PAE is not enabled

 

2 MB pagination not enabled for PAEPage table structure

 

Enable 4 K paging for PAEPage table structure

 

Enable 2 MB pagination under PAEPage table structure