Preemptible priority and response priority in STM32, and stm32 priority

[Switch] preemptible priority and response priority concepts in STM32, and stm32 priority

 
STM32 (Cortex-M3) has two priority concepts-preemptible priority and response priority, some people call the response priority as 'subpriority 'or 'subpriority ', each interrupt source must be assigned these two priorities.
 
An interrupt with a high preemptible priority can be responded to during interrupt processing with a low preemptible priority, that is, interruption nesting, or a high-preemptible interrupt can be nested in a low-preemptible interrupt.

When the preemptible priorities of the two interrupt sources are the same, there is no nested relationship between the two interrupts. When one interrupt arrives, if another interrupt is being processed, the resulting interruption will not be processed until the previous interruption is completed. If the two interrupts arrive at the same time, the Interrupt Controller determines which one to process based on their response priority. If both their preemptible priority and response priority are equal, then, they decide which one to process first based on their ranking order in the interrupt table.

After reading the above introduction, I believe everyone understands the relationship here. The summary is as follows: preemptible priority> response priority> the ranking order in the interrupt table (">" is considered as the direction of comparison ).

It is precisely because each interrupt source needs to be specified with these two priorities that a corresponding register bit is required to record the priority of each interrupt; in the Cortex-M3, 8 bits are defined to set the priority of the interrupt source, which can have 8 allocation methods, as shown below:

1. All 8 bits are used to specify the response priority.

2. The maximum value of 1 is used to specify the preemptible priority, and the minimum value of 7 is used to specify the response priority.

3. The maximum two bits are used to specify the preemptible priority, and the lowest six bits are used to specify the response priority.

4. The maximum three bits are used to specify the preemptible priority, and the lowest five bits are used to specify the response priority.

5. The maximum 4 bits are used to specify the preemptible priority, and the minimum 4 bits are used to specify the response priority.

6. A maximum of five bits are used to specify the preemptible priority, and a minimum of three bits are used to specify the response priority.

7. A maximum of 6 bits are used to specify the preemptible priority, and a minimum of 2 bits are used to specify the response priority.

8. The maximum 7 bits are used to specify the preemptible priority, and the lowest 1 bits are used to specify the response priority.

The above is the concept of priority group, but the Cortex-M3 allows to have a less interrupt source with a smaller register bit to specify the priority of the interrupt source, so STM32 to specify the interrupt priority of the register bit to four, the four register bit grouping methods are as follows:

Group 0th: all four bits are used to specify the response priority.

Group 1st: the maximum value of 1 is used to specify the preemptible priority, and the minimum value of 3 is used to specify the response priority.

Group 2nd: the highest two bits are used to specify the preemptible priority, and the lowest two bits are used to specify the response priority.

Group 3rd: The maximum three bits are used to specify the preemptible priority, and the lowest one is used to specify the response priority.

Group 4th: all four bits are used to specify the preemptible priority.

The NVIC_PriorityGroupConfig (u32 NVIC_PriorityGroup) function is related to the firmware library that is most prerequisite in the article. There are five function parameters:

The parameter (NVIC_PriorityGroup value) of this function has the following five types:

NVIC_PriorityGroup_0 => select 0th groups. // All are response priorities. All interrupts cannot be preemptible.

NVIC_PriorityGroup_1 => select 1st groups // two preemption priorities

NVIC_PriorityGroup_2 => select 2nd groups // four preemption priorities

NVIC_PriorityGroup_3 => select group 3rd // eight preemption priorities

NVIC_PriorityGroup_4 => select 4th groups/16 preemption priorities without response priorities. All interruptions can be preemptible based on their priorities.

This is actually quite understandable. For example, if NVIC_PriorityGroup_1 is selected, the preemptible priority takes one place. That is to say, there can be 2 ^ 1 levels, which can be set to 0 and 1, the response priority occupies three places, that is to say, there can be 2 ^ 3 options, which can be set to 0 ~ 7; in total, it can be different> 16 priorities (why is it greater than or equal to, you should understand it)

For example, if there are four external interruptions and an EXTI9_5 interrupt, if the priority group is set to 1st, there are only two preemptible priorities, at least three of the five interruptions have the same preemptible priority, and the other two have the same priority. There are eight options for setting the response priority. If there are two preemptible interruptions with the same priority, the priority of the response is higher, and the priority of the response is higher, in addition, this should be noted. If another interrupt with the same preemptible priority but higher response priority comes after the interrupt, the existing interrupt will not be interrupted.