Relationship between BIOS and EC

Recently, looking at the bios of the relevant content, has emerged an EC concept. Internet search for relevant content, organized the next, the BIOS and the relationship between the EC

The status of the BIOS (basic input and output system) in the entire system is very important, and it is implemented as a bridge between the underlying hardware and the upper operating system. For example, if you are copying a file from a disc to a hard disk, you only need to know the "copy and paste" instructions, and you don't have to know how it is read from the disc and then how to write to the hard disk. For the operating system, it is only necessary to issue instructions to the BIOS, without knowing how the disc is read and how the hard disk is written. The BIOS builds a bridge between the operating system and the underlying hardware. The BIOS settings We usually say only refer to the settings of their software, such as setting the boot order, disabling/enabling some features, and so on. But here's a question, how is the BIOS implemented on the hardware? After all, is the software running on a hardware platform? What we cannot fail to mention here is EC.

EC (Embed controllers, embedded controller) is a 16-bit microcontroller, it also has a certain amount of flash inside itself to store the EC code. EC's position in the system is no more than that of the north-south Bridge, which controls the timing of most important signals during the system's opening. In the notebook, the EC is always on, whether you are on or off, unless you remove the battery and the adapter completely. In the Shutdown state, the EC keeps running and waits for the user's boot information. And after the boot, the EC is more as a keyboard controller, charging lights, as well as fans and various other indicators such as the control of equipment, it even control the system's standby, hibernation and other states. In the mainstream notebook system

Now the EC has two architectures, more traditional, that is, the bios of flash through the X-bus to the EC, and then the EC through LPC to the South Bridge, in general, the EC code is also placed in Flash, that is, and the BIOS shared a flash. On the right is a newer architecture, with the EC and flash co-connected to the LPC bus, which typically uses only the internal ROM of the EC. As for the LPC bus, it was the bus standard that Intel had introduced in order to replace the low-speed, backward x-bus. The EC generally contains a keyboard controller, so it is also called KBC. What is the implications of the EC and BIOS work in the system? Here, let's start with a simple analysis. When the system shuts down, only the RTC part and the EC part are running. The RTC section maintains the computer's clock and CMOS setup information, while the EC waits for the user to press the power button. When the user presses the power-on key, the EC notifies the entire system to turn it on, and after the CPU is reset, it reads the instructions within a specific address within the BIOS (actually a jump instruction, which is set by the CPU hardware). This starts in two cases, the 1 CPU sent this address through the FSB to the North Bridge, and then through the Hub-link to the South Bridge, through the LPC to the EC, and then through the X-bus has reached the BIOS. After the CPU reads the instruction within the issued address, it executes the first instruction after reset. In this system, the EC plays the role of bridging the BIOS and the South Bridge (or the entire system), and after the CPU sends the address to the South Bridge, it is directly through the LPC to the BIOS and does not require an EC bridging.
It is important to note that the EC is generally not required for desktops. There are many reasons for this: for example, the desktop itself ATX Power has a certain intelligence function, he has been able to be controlled by the operating system to achieve standby, hibernation state; second, since the notebook keyboard can not be directly connected to the PS/2 interface, but must be connected to the EC, and the notebook has more small functions, such as charging indicators , WiFi indicator, FN and many other special functions, and the notebook must support the battery charge and discharge functions, and intelligent charge and discharge needs EC support; In addition, the switch timing of the notebook TFT screen must also be controlled by the EC. These reasons have led to the need for notebooks to use EC for internal management.
Overall, both the EC and the BIOS are at the bottom of the machine. The EC is a separate processor that manages the entire system in the pre-boot and boot-up process. The BIOS starts running after the EC has initialized the internal physical environment.
See here, I think we also understand that EC is the holy side. If the BIOS is the underlying system, then the EC seems to be much lower.

In the South Bridge there is also a function block is the Power Management Unit (Pm,power Management), in general, he and EC to work together to complete. This includes all functions of the boot, standby, hibernation, shutdown from the power-on button. Also includes the backlight brightness, sound and so on control and so on. As for Intel's speed step technology, some of the features are implemented via the South Bridge (the South Bridge sends SLP, STPCLK (Sleep,stop Clock) for sleep, deep sleep, etc.).
This part of the design is relatively simple, only need to point to the South Bridge and the CPU.

Logical start-up process:
The boot process is essential for computer design. When the laptop is on the PCB after the first boot, if the timing of the power supply is correct, the other problems are relatively good solution (usually the correct timing of the machine can be opened up). The most feared is the power supply timing is not correct, the machine can't open, this is the most deadly. There are several voltages inside the notebook, first the RTC power supply, which is never turned off unless the battery (coin cell) is out of power and does not pick up any external sources (such as batteries and power adapters). RTC is used to keep the internal clock of the machine running and to ensure that the CMOS configuration information is not lost in the case of power failure, and secondly, when you plug in the battery or the power adapter.

But did not press the Power key when (S5), the machine inside the power of the electric called always, mainly to ensure the normal operation of the EC;
Again, after you turn on, all the power is turned on, this time, we call main power (S0), for the whole machine to run;
When you enter the standby (S3), the machine internal power becomes SUS power, mainly DDR power supply to ensure that the internal RAM data is not lost;
While the power of Sleep (S4) and shutdown (S5) is the same, it is always power. Where the above brackets indicate the state of the computer (s0-boot, s3-standby, s4-hibernation, s5-shutdown).

Now that we assume that there is no power supply (no batteries and no power), then only the RTC circuit is operating inside the machine, and a 3V button battery will be supplied to RTC power to keep the internal time running and CMOS information.

        South Bridge start-up timing  

        based on the previous power Status, let's analyze the boot process. When the battery or power is plugged in, the SCM EC on the inside of the machine is reset and starts to work, waiting for the user to press the Power key. The timing for this period is: After the always power is switched on, the EC reset and starts to run, and then sends a signal called ' rsmrst# ' to the South Bridge. At this time, some functions of the South Bridge begin to initialize and wait for the start signal. Note here that the South bridge at this time does not have all the power, only a small part of the function is available, such as the pwrbtn# signal for detecting the boot signal.  
      When the user presses the Power key, the EC detects a level change (the general timing is: high-low-high), then sends a start-up signal (pwrbtn#) to the South Bridge, The South Bridge received pwrbtn# signal, pull high slp_s5#,slp_s4#,slp_s3# signal, turn on all the peripheral voltage, mainly +3v,+5v and ddr2.5v, and send PM Pwrok signal, this signal indicates that the peripheral power is open normally.  
        PM Pwrok will act as an enable signal to the VCCP voltage generator of the CPU perimeter and turn on VCCP. After this, the VCCP generator will issue core_vr_on to open the core VR (that is, the central voltage of the CPU). At this point, the entire voltage has been opened.  
        in the signal with Vr_pwrgd_ich to notify the South Bridge Core VR successfully opened, the South Bridge will issue a PCI rst# signal to the PCI bus, The device on the bus is initialized (including the North Bridge), and the H_PWRGD is issued to inform the CPU that its core voltage has been successfully turned on. Then North Bridge issued h_cpurst# signal to CPU,CPU was reset, and formally began to work.  
        when users need to enter Standby mode (S3), the system ACPI and Windows work simultaneously, pulling down slp_s3# and keeping slp_s4 #和SLP_S5 # is pulled high to turn off the main power, the system goes into standby mode.

While you need to go into hibernation or shutdown mode, pull down slp_s3#, slp_s4#, and slp_s5# at the same time, turning off the power supply except RTC. Of course, in this series of processes, the operating system and the BIOS need to work together, for the hardware, only need to ensure that a specific state of the voltage supply.
When the machine to enter the S5 from the S0, that is, the shutdown, there will be a certain timing, basically is the inverse of the previous sequence.

The above is the entire hardware boot, into the S3,S5 process, of course, different hardware has different boot process, here is just the most common, the most frequent one ACPI is the Advanced Configuration and Power interface abbreviation, meaning " Advanced Configuration and Power interface. This is a power management standard developed jointly by Intel, Microsoft, and Toshiba.
ACPI enables the following features:
1, the user can make the peripheral at a specified time switch;
2, the user of the notebook computer can specify that the computer in low-voltage situation into the low-power state, to ensure that important applications run;
3, the operating system can reduce the time requirements of the application of the case of low clock frequency;
4, the operating system can be based on the specific needs of peripherals and motherboards to allocate energy for it;
5, when no one uses the computer can put the computer into hibernation, but to ensure that some communication devices open;
6. Plug and Play devices can be controlled by ACPI when plugged in.
However, ACPI and other power management methods, in order to enjoy the above features, you must have software and hardware support. In terms of software, both Windows 98 and its successor products and Windows 2000 all have full support for ACPI, and the Linux kernel is not so well supported at this time. Hardware is more troublesome, in addition to the motherboard, graphics card and network cards and other peripherals to support ACPI, but also need chassis power to cooperate. Power supply in the 5 volt to the motherboard, but also to stabilize the current at more than 720 ma, so that it can achieve the computer's "sleep" and "Wake up."
ACPI has six states, namely S0 to S5, which represent the following meanings:
s0--In fact, this is our normal working state, all the equipment fully open, power consumption will generally exceed 80W;
s1--is also known as POS (Power on Suspend), in addition to the CPU clock controller to turn off the CPU, the other parts are still working normally, the power consumption is generally below 30W; (actually some CPU cooling software is to use this principle of operation)
s2--the CPU is in a stopped state and the bus clock is turned off, but the rest of the device is still functioning;
s3--This is our familiar str (Suspend to RAM), when the power consumption does not exceed 10W;
s4--also known as STD (Suspend to disk), when the system main power is off, but the hard disk is still charged and can be awakened;
s5--This state is the simplest, all the devices, including the power supply, all shut down, the power consumption is 0.
Our most common use is the S3 state, which is the suspend to RAM (suspended to memory) state, referred to as Str. As the name implies, STR is to put the system into the working state of STR before the data are stored in memory. In the STR state, the power supply continues to power the most essential devices such as memory to ensure that the data is not lost, while the other devices are turned off, and the system consumes very little. Once we press the power button (the host power switch), the system is awakened, reading the data from memory immediately and reverting to the working state before Str. Memory reads and writes are extremely fast, so we feel that it takes only a few seconds to enter and leave the STR state, whereas the S4 state, the STD (suspend to hard disk), is exactly the same as the STR, except that the data is stored on the hard disk. Because the hard disk reads and writes much slower than memory, it is not as fast as Str. The advantage of STD is that it can be implemented only through software, such as Windows 2000, which can implement STD on hardware that does not support Str.
Before power Management is APM (Advanced Power Management), what is the difference between ACPI and APM?

2. ACPI VS APM Comparison
APM 1.0&1.1: Power management performed by the BIOS;
APM 1.2: The operating system defines the power management time, which is performed by the BIOS;
Acpi:bios collects hardware information, defines a power management scheme, and is executed by the operating system.
APM is a software solution that is related to the operating system, and ACPI is an industry standard that includes both software and hardware specifications.

The APIC (Advanced Programmable Interrupt Controller) has two functions for a computer,
One is to manage the allocation of IRQ, the traditional 16 IRQ can be extended to 24 (traditional management method called pic) to adapt to more devices.
The second is to manage multiple CPUs. Since the NF2 motherboard does not support multiple CPUs, the direct effect of APIC shutdown is to reduce the available IRQ.
However, if the board is not very much, shutting down the APIC has no effect on the system.
To implement the SMP feature, the CPU we use must have the following requirements:
The APIC unit must be built inside the CPU. The core of the Intel Multi-processing specification is the use of Advanced Programmable Interrupt controllers (Programmable Interrupt controllers--apics). The CPU communicates between them by sending interrupts to each other. By giving the interrupt additional actions (actions), different CPUs can control each other to some degree. Each CPU has its own APIC (the local APIC of that CPU), and there is an I/O APIC to handle interrupts caused by I/O devices, the I/O APIC is installed on the motherboard, but the APIC on each CPU is indispensable, Otherwise, you will not be able to handle interrupt coordination between multiple CPUs.
APIC may be experiencing problems that many of these issues can be resolved through a BIOS update.
The following is done by changing the HAL type to resolve
CPU actual operating frequency does not match the BIOS setting frequency
About 10% of NF2 users will experience a problem where the CPU's actual operating frequency does not match the BIOS setting frequency. We call it "the wrong frequency."
The direct result of this phenomenon is that when testing 3DMark or running 3D games, it will feel not smooth, also known as "Dayton."
Generally after changing the BIOS settings, after the update driver restart, with the test software such as AIDA32, MBM5, etc. can see the CPU running frequency and you set in the BIOS is not the same, and the gap is very large. This time, using Super PI Test CPU speed, will take longer than usual time to spend a few seconds, with 3DMark run test, will be hundreds of points or even thousands of points lower than usual. The CPU frequency seen in 3DMark also does not conform to the BIOS settings.
If this is the case, then we are talking about the "frequency of the wrong" issue.
However, not all 3D games "Dayton" are for this reason. The method of judging is: if you only have individual game "Dayton", or use the above software test frequency is correct, this is not the problem.
If the judgment is really this problem, the solution is also very simple, after discussion by netizens, as long as the switch off the APIC function. (Note that it is APIC, not ACPI.)

Relationship between BIOS and EC