STM32F103X Datasheet Study Notes---GPIOs and afios

1. Preface

Each GPIO port has several registers to operate on:

• Two 32-bit configuration registers: GPIOX_CRL, GPIOX_CRH
• Two 32-bit data registers: GPIOX_IDR, GPIOX_ODR
• One 32-bit set/reset register: GPOX_BSRR
• One 16-bit reset Register: GPIOX_BRR
• One 32-bit lockout register: Gpiox_lckr

Note: GPIO_BRR and GPIO_BSRR Support read-write atomic access

The port of each set of Gpio can be configured as the following IO mode:

2.GPIO Basic Structure

Figure standard GPIO BITS basic structure

Figure Port Bit Configuration table

Figure output Mode bit

3.GPIO Function Description 3.1 general purpose IO (GPIO)

• Reset in process or after reset

The optional function of the PIN is invalid, and the port is configured as input floating Mode (cnfx[1:0]=01b, modex[1:0]=00b).

Reset Rear Jtag Pin:PA15:JTDI in Pu, pa14:jtck in PD, Pa13:jtms in Pu, Pb4:njtrst in Pu

• Configure as output mode

The value written to the GPIOX_ODR is output to the port pin, which may be used for drive mode: Push-pull or Open-drain

• Configure as input mode

GPIOX_IDR captures the data on the IO pins at each APB2 clock cycle

Note: 1. Each GPIO pin has a weak pull-up and a weak drop-down, which can be determined when configured as input mode to enable

• Bit set/reset of atoms

There is no need to turn off interrupts when operating the GPIO_ODR register by writing the GPIO_BRR or GPIO_BSRR to the associated port bit of the set or reset Gpio

STM32F103X Datasheet Study Notes---GPIOs and afios