The relationship between the pre-loaded register of the STM32 timer and the Shadow register "go"

First reproduced: Relationship between pre-loaded registers and shadow registers of the STM32 timer

The instructions in this document are based on the STM32 Reference Manual (RM0008) version 10th:
English: Http://www.st.com/stonline/products/literature/rm/13902.pdf
Chinese translation: Http://www.stmicroelectronics.com.cn/stonline/mcu/images/STM32_RM_CH_V10_1.pdf

In the 13th and 14 chapters of the STM32 reference manual, there is a block diagram of the timer, the following is the part of the timer block diagram in the 14th chapter, the Yellow box shown is auto-reload register, in the following 14th. 3.2 "Counter Modes" It explains the usage of the Auto-reload register.

You can see the Auto-reload register in the diagram. This box has a shadow, and some other registers are also useful for shadow representations, such as the Capture/compare register that I marked with blue, and a shaded register that indicates that the register corresponds to 2 registers physically. One is a register that programmers can write or read, called the Preload Register (preload register), and the other is a register that the programmer does not see but actually works in the operation, called the Shadow Register (shadow register) As described in section 14.3.1 of the manual, the contents of the preload register can be transmitted to the Shadow register at any time according to the APRE bit settings in the TIMX_CR1 register, i.e., the two are connected (permanently), Or, the contents of the preload register are transmitted to the Shadow register at the time of each update event (Uev).

An uppercase u and a downward arrow in a red line circled in the graph, indicating that the shadow Register of the corresponding register can be updated to the contents of its preload register when an update event occurs, while the portion of the figure with the green coil indicates the corresponding autoreload Register can produce an update event (U) or an update event interrupt (UI).

The benefit of designing the preload register and the shadow register is that all registers that really need to function (shadow Register) can be updated to the content of the corresponding preload register at the same time (when an update event occurs). This ensures that the operation of multiple channels can be accurately synchronized. If there is no shadow register, or preload register and shadow register are passthrough, that is, the software updates preload register, the shadow Register is also updated, Because the software cannot update multiple registers at the same time, the sequence of multiple channels cannot be synchronized, and if other factors (such as interrupts) are added, the timing relationship of multiple channels may be unpredictable.

(Original file name: stm32_tim_auto_reload_register.gif)

Personal Comments:

1. There are 3 Shadow registers: The Crossover register PSC, automatically reloads ARR, automatically captures the CCRX, note that PSC,ARR,CCRX is not a shadow register, but the corresponding "preloaded register";

2, the shadow register is the real function of the register, but St does not provide this register out, just provide the corresponding preload register, respectively, "PSC,ARR,CCRX"

3, our users can access, can modify or read the pre-loaded registers, St Just open them out (the shadow register is not open to the user), in fact, is the ARR register, such as: Tim1->arr

4, from the pre-loaded register arr to the shadow register, there are two ways, one is immediately updated, one is the update after the trigger event, which mainly depends on the register TIMX->CR1 "apre" bit;

4.1, Apre=0, when the ARR value is modified, the value of the shadow register is updated immediately;

4.2, apre=1, when the ARR value is modified, the value of the shadow register must be updated after the next event Uev occurs;

5, how to immediately change the shadow register value, not the next event;

5.1, will Arpe=0,tim_arrpreloadconfig (Ch1_master_tim, DISABLE);

5.2 In Arpe=1,tim_arrpreloadconfig (Ch1_master_tim, ENABLE); After we have changed the preloaded registers, we immediately set the Uev event, that is, to change the UG bit of EGR storage, as follows:

Tim1->arr = period-1; Set cycle
TIM1->CCR1 = period>>1; Set duty ratio 50%
Tim_generateeventtim1,tim_eventsource_update); Take the initiative to Uev events, ug=1

6. The transmission process is as follows:

The relationship between the pre-loaded register of the STM32 timer and the Shadow register "go"