With the help of software, you can go to linux for PCB-general Linux technology-Linux programming and kernel information. The following is a detailed description. My bashrc is as follows
# Cadence PSD environment icq 111290069.
Due to early contact and use, there are a large number of Protel users in China. While selecting the High-Speed PCB solution for Cadence, they all face the problem of how to port the Protel design at hand to the Cadence PCB design software.
The problems encountered in this process can be roughly divided into two types: one is that the design is not very complex, the designer just wants to use the powerful Automatic wiring function of Cadence CCT to complete the wiring work; the other is that the design is complex, designers need to use noise analysis tools to simulate the design and set the wiring topology of the network.
In the first case, the conversion work is relatively simple. You can use the Protel to CCT conversion tool provided by Protel or Cadence to complete this work. In the second case, the work to be done is relatively complicated. The following describes the conversion method.
Chenqs@clo.com.cn
The analysis object of the Cadence noise analysis tool is the brd file of Cadence Allegro, and Allegro can read the required third-party network table, the Network tables in Telexis format output by Protel meet the requirements of Allegro for third-party network tables, so that the Protel file can be injected into Allegro.
There are two points for your attention. First, Allegro third-party network tables in the $ PACKAGE segment do not allow ". in Protel, we use BasName [0: N] to represent the bus and BasName [x] to represent a signal in the bus, the expression of a signal in the bus in the Allegro third-party network table is Bas NameX. You can directly modify the Telexis network table output by Protel to solve these problems.
Allegroat returns the device.txt file for each device in the third-party network table. The format is as follows:
Package: package type
Class: classtype
Pincount: total pinnumber
Pinused :...
PACKAGE, CLASS, and PINCOUNT are commonly used. PACKAGE describes the encapsulation of the device, but Allegro uses the PACKAGE item in the network table when injecting the network table, ignoring this item in the device description file. CLASS determines the device type for noise reduction. Cadence divides the device into three categories: IC, IO, and DISCRETE. PINCOUNT indicates the number of pins of the device. For the devices, the device.txt file contains these three items.
With the third-party network table and device description file, we can import the schematic design in Protel into the Cadence PCB design software in the form of a network table. Next, designers can use the powerful features of Cadence PCB software in high-speed and high-density PCB design to complete their own design.
If you have already done PCB layout in Protel, The script Function of Allegro can reproduce the layout in Protcl in Allegro. In Protel, the designer can output A Place & Pick file, which contains information about the position, rotation angle, top layer, and bottom layer of each device, you can use this file to easily generate an Allegro script file, and execute this script in Allegro to reproduce the layout in Protel, the following provides the C ++ code for converting the Place & Pick file to the Allegro Script file. The author uses this code, it takes only several minutes to reproduce the PCB layout of more than 800 devices for a user in Allegro.
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