Verilog代碼自動縮排和對齊Perl指令碼

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實驗室做FPGA開發時經常用到Verilog，代碼規範成為一個問題，於是乎寫了一個Perl指令碼對代碼進行正常化，主要是進行自動縮排和對齊。

代碼原理很簡單，主要是使用了Regex進行匹配和替換。

代碼如下，初學Perl，請讀者賜教：

###################################################### 代碼縮排對齊指令碼# 功能：對Verilog代碼進行自動縮排和對齊處理，#該版本目前還沒有對case語句進行處理# 更改：增加了對assign的縮排# 運行環境：perl# 運行方式：perl code_indent.pl# 段聰# 日期：2014/9/16 22:16#####################################################my $filename = ‘C:\Users\CvCv\Desktop\Perl_tmp\code.v‘;#輸入檔案名稱my $outfilename = ‘C:\Users\CvCv\Desktop\Perl_tmp\out.v‘;#輸出檔案名#----------------------------------------------------------#測試檔案存在die "檔案$filename不存在！\n" unless -e $filename;#開啟檔案open(VFILE,"<",$filename) || die "開啟檔案失敗!\n";open(OFILE,">",$outfilename) || die "開啟檔案失敗!\n";#----------------------------------------------------------#變數定義$begin_cnt = 0;$if_cnt = 0;$autoindent_space = " "x4;#自動縮排的空格數（Tab寬度）$last_line = "";$assign_start = 0;#----------------------------------------------------------#讀取並處理檔案while(<VFILE>){$line = $_;if(/\s*\b(input|output|reg|wire)\b/i){$line =~ s/^\s+//;my @result = ($line =~ /\s*(input|output|reg|wire|(?:output\s+reg))\s*(\[\d+\:\d+\])?\s*((?!reg|wire)\w+)([,;]?)/ig);#print length($result[0]),"[email protected]\n";if($#result>0){$line  = $result[0]." "x(20-length($result[0]));$line .= $result[1]." "x(20-length($result[1]));$line .= $result[2]." "x(20-length($result[2]));$line .= $result[3]."\n";}$last_line = $_;}elsif(/(parameter)?\s*(\w+)\s*\=\s*(\d+\‘[hbHB][0-9a-fA-F_]+)\s*([,;]?)/i){$line =~ s/^\s+//;my @result = ($line =~ /(parameter)?\s*(\w+)\s*\=\s*(\d+\‘[hbHB][0-9a-fA-F_]+)\s*([,;]?)/ig);#print $#result."[email protected]\n";if($#result>0){$line  = $result[0]." "x(20-length($result[0]));$line .= $result[1]." "x(35-length($result[1]));$line .= "= ".$result[2]." "x(18-length($result[2]));$line .= $result[3]."\n";}$last_line = $_;}elsif(/\s*\b(module|endmodule|always|assign)\b/i){#匹配到module|always|assign$line =~ s/^\s+//;if(/\s*\bassign\b\s+\w/i){#匹配到assign$line =~ s/\s*\bassign\b\s+(\w)/assign  $1/i;$assign_start = 1;#print;}$last_line = $_;}elsif(/\bbegin\b/i){#匹配到begin$begin_cnt++;my $tmp_space = $autoindent_space x $begin_cnt;$line =~ s/^\s*/$tmp_space/;$last_line = $_;}elsif(/\bend\b/i){#匹配到endif($if_cnt>0){$if_cnt--;}my $tmp_space = $autoindent_space x $begin_cnt;$begin_cnt--;$line =~ s/^\s*/$tmp_space/;$last_line = $_;}elsif(/\bif\s*\(/i){#匹配到if$if_cnt++;my $tmp_space = $autoindent_space x ($begin_cnt>0?($begin_cnt+1):$begin_cnt);$line =~ s/^\s*/$tmp_space/;$last_line = $_;}elsif(/\belse\s*/i){#匹配到elsemy $tmp_space = $autoindent_space x ($begin_cnt>0?($begin_cnt+1):$begin_cnt);$line =~ s/^\s*/$tmp_space/;$last_line = $_;}elsif(/^\s*$/){#匹配到空行$line = "\n";}else{#print $if_cnt,"--",$_;if($assign_start){my $tmp_space = $autoindent_space x2;$line =~ s/^\s*/$tmp_space/;if(/".*;\s*$"/){$assign_start = 0;}}elsif($last_line =~ /(\bif\s*\()|(\belse\s*)/){$if_cnt--;my $tmp_space = $begin_cnt>0 ?  ($begin_cnt+2):$autoindent_space;$line =~ s/^\s*/$tmp_space/;}else{my $tmp_space = $begin_cnt>0 ? $autoindent_space x ($begin_cnt+1):"";$line =~ s/^\s*/$tmp_space/;}$last_line = $_;}$text.=$line;}#關閉檔案close VFILE;select OFILE;print $text;close OFILE;select STDOUT;print "處理完畢，檔案輸出到$outfilename\n";

Verilog代碼自動縮排和對齊Perl指令碼