Major manufacturers to develop, chip-solid stacking technology application is imminent

TSV Stereo Stacking technology has been emerging in a variety of applications. TSV Stacking technology is used in DRAM, FPGA, wireless equipment and other applications, can enhance its performance and maintain low power consumption, thus gaining the favor of semiconductor plant and analog components factory, however, to accelerate the speed of TSV technology in the market, still need to rely on behalf of factories, IP vendors, EDA plant and the plant to seal the work of cooperation.

The previous article has analyzed how to apply the silicon perforation (TSV) to the stereo stacking when the image sensor, the power amplifier and the processor and so on the present situation and the forecast, therefore this issue will continue the discussion in the last period, then covers the popular commodity application, lets the reader be possible to be clearer about the future trend

TSV grab into the hot app market

Today's portable devices almost everything in the palm of the hand, as long as a button, you can browse the Internet, email, watch High-definition TV or use the Global Positioning System (GPS) services. Multimedia needs more and more, but also make the design more and more complex, designers all want to continue to narrow the pin structure to achieve better function, but less power consumption.

Because of the increasingly urgent need for portable computing, the industry began to pursue more advanced memory technology, allowing portable devices to support three-dimensional (3D) stereo games and Family Theater standard 1,080p, 60 video devices per second, and other capabilities. In the 2013, the design of a single crystal chip (SoC) for a portable equipment system would require more than 10GBIT/S's memory bandwidth performance specification. In addition, the use of the TSV 3D IC concept to improve power consumption and efficiency while looking for better memory technology and improved pin size in a portable industry is a viable direction (Figure 1).

Fig. 1 Technical blueprint for 3D IC packaging using stacked wafer and TSV technology

For the wide input/output (Wide I/O) interface, application of TSV stack dynamic random access memory (DRAM) on a logical chip, it can be two to four times times faster than the LPDDR2 technology in the case of half the power consumption per bit, which is really a big incentive for the industry, The current application status is described below.

Apply to DRAM

On DRAM memory, Delta (Elpida), Samsung (Samsung) and (Micron) have now started to supply DRAM samples using TSV stacks, and these three companies have published many stacked concepts with Boon Jubilee (NEC) and Oki Tepco. The technique used to stack dram is, of course, for efficiency, power saving and size.

IBM's research points out that when it comes to extending the DDP (Dual Die Package) to support 1,333mbit/s or even to 1,600mbit/s, the TSV technology will eventually be needed because the technology can be used without line-bonding (Wire bonding), The DRAM stacking package is smaller in size and has faster data transfer capabilities and bandwidth.

The declared bankruptcy of Seoul, as early as 2009, has successfully developed multilayer copper TSV stacked 8Gb dram memory, this DDR3 SDRAM can have 1,600mbit/s operating rate, and in the core layer has 1,030 interconnection (a single package of 8,357 convex block interconnect, Contains the interface layer, the maximum height of the package is only 1.3 mm (mm), which contains eight core layer and an interface layer, the current 8Gb TSV DRAM has begun to provide, and soon you can see 16Gb products (eight layers of 2Gb of DRAM products) appear.

In the case of an integrated component manufacturer (IDM), Samsung has the ability to develop 3D ICS, and market news points out that over the years Samsung has extended its packaging technology to different applications, and its 3D DRAM structure can now support four rank movements, Includes one master (master) and three slave-end (Slave) wafers, and uses nearly 300 TSV, which support functional modularity and provide a buffer module solution in which the master chip is a four-piece 2Gb DDR3 DRAM, And another control loop of more than rank, and the slave chip has 2Gb memory core and wafer-level test circuit, the density of the components of a total of 8Gb, and each stack can form a rank,master chip can be used as an insulated channel (Channel) and slave chip between the buffer , so that the input/output data can be transferred to the 1,600mbit/s in a structure with four rank/module and two module/channel, but if the traditional QDP (Quad Die Package) structure is used, the transmission rate can only reach 1. 066mbit/s.

Manufacturing for high-performance computer equipment, such as server manufacturers, is also interested in improving space for TSV technology. According to IBM, server memory capacity is growing at least twice times per generation, and because consumers ' preference for a smaller system size limits the total number of memory slots and allows memory module density to be elevated, a good way is to use 3D TSV Technology manufactures a DRAM high order application of the server.

JEDEC Solid State Technology Alliance announced in 2012 a new action DRAM standard--jesd229 Wide I/O single Data Rate (SDR). Because the wide I/O action DRAM is a breakthrough technology to meet the industry's need to increase the level of integration and improve bandwidth, latency (latency), power supply, weight and size, so that smart phones, tablets, handheld games consoles and other portable components can be effective, The ultimate performance of power saving and size reduction, the main requirement of this standard is to use the TSV 3D stacking ability, the memory chip directly stack interconnect to a single system of the standard required, it defines the relevant properties, Functions, AC (AC) and DC (DC) values and ball/signal configuration, Particularly suitable for applications that require excellent power consumption and greater memory bandwidth (max to 17gb/s), examples of applications include 3D games, high-resolution video files, or multiple applications at the same time, compared to the previous generation of standard LPDDR2, at the same power consumption level, Wide I/O bandwidth is about twice times wider.

Target FPGA Market

Using the advantages of 3D structure on logical elements, the most advantageous evidence is in the application of Field Programmable gate Array (FPGA). The traditional FPGA contains a bunch of simple and programmable logical component arrays, and there is a programmable interconnection structure, so you can according to the requirements of the system designers to draw the logical block of the connected structure, but the efficiency of the FPGA is accounted for 90% of the chip area of the interconnect structure, and will result in 40%? 80% component delay.

3D Integrated Technology Thus found this application, because it can help FPGA to remove the programmable interconnect structure from the logical block, instead of the other layers of the stack, thereby reducing the original interconnect delay phenomenon, but can be used on the FPGA 3D TSV, It is still necessary to see whether the wafer generation plant has a corresponding design tool and the ability to apply TSV to the 300 mm wafer.

Industry standards are another issue, for example, and there are still many discussions about developing a standard for manufacturability design (DFM) or testability design (DFT) in 3D design. The 3D Test sharable Group of the American Institute of Electrical and Electronic Engineers (IEEE) presents the IEEE 1838 standard, which is intended to define the infrastructure and description language that can be used as a test architecture in a 3D component, which is critical Because it can be used to test and confirm the quality of 3D components in IC process, it is very important for FPGA to apply 3D technology.

Enhance wireless device performance

Companies that supply wireless devices see TSV as the most promising solution for increasing processor performance, hardening the bandwidth between processors and memory, improving data access, limiting battery power, low cost, and miniaturization.

However, the current packaging technology is limited to the use of wire bonding or laminating technology to do three-dimensional stacking, in some applications, also tend to use POPs (Package on Package) or Pip (Package in Package) and other technologies, and COC (Chip on Chip) also because it can not fully meet all the needs, but only used in some applications, so in this application, the future has absolute market space can be developed.

In addition to the above applications, TSV also attracted interest from other semiconductor plants, for example, analog component suppliers also regulate the use of TSV, mainly to shorten the design time to quickly market (about 18 months), mainly because there are existing design tools can also be used, and TSV connecting components, You can also mix technologies or use different technology nodes (Marvell node), such as a wafer portion that can be designed using 130 nm node technology, or 45 nm technology in other parts, which can be very effective in this case, For example, you can optimize the technology of digital components, but not necessarily the optimization of analog components, mixing different nodes can be used to improve the flexibility of integration.

In addition, because the total length of the chip interconnect is shortened and has lower capacitance, it can also reduce the power consumption and improve the speed efficiency. However, the disadvantages of TSV applied to mixed digits and analog elements may include the interaction between the analog chip and the High-frequency digital element, and the interference of electromagnetic and RF (RF). Then, we discuss the current predictive data of these applications in the market.