----PHY Configuration of Linux network subsystem

Mii is the media independent interface, also known as Media independent interface.

It includes a data interface and a management interface between Mac and PHY (Figure 1).

The data interface includes two separate channels for transmitters and receivers, respectively. Each channel has its own data, clock, and control signals. The MII data interface requires a total of 16 signals.

The management interface is a two-signal interface: one is a clock signal and the other is a data signal. Through the management interface, the upper layer can monitor and control phy.

The Rmii port uses two wires to transmit the data,

The MII port uses 4 wires to transmit the data,

The gmii is used to transmit data with 8 wires.

GMII (Gigabit MII)

The gmii is a 8bit parallel synchronous transceiver interface with 8-bit interface data and a working clock of 125MHz, thus transmitting rates up to 1000Mbps. Compatible with the 10/100 Mbps operating mode as defined by Mii.

The Gmii interface data structure conforms to the IEEE Ethernet standard. The interface definition is shown in ieee802.3-2000.

Transmitter:

◇gtxclk--Gigabit TX.. Signal Clock signal (125MHZ)

◇txclk--10/100m Signal Clock

◇txd[7..0]--is sent data-------Mii is 4, so one channel is 8, and two is 16.

◇txen--transmitter Enable signal

◇txer--transmitter error (used to destroy a packet)

Note: At gigabit rates, the GTXCLK signal is provided to the PHY, and the TXD, Txen, and txer signals are synchronized with this clock signal. Otherwise, at the 10/100m rate, the PHY provides a TXCLK clock signal, and the other signals are synchronized with the signal. The operating frequency is 25MHz (100M network) or 2.5MHz (10M network).

Receiver:

◇rxclk--receive clock signal (extracted from received data, therefore not associated with GTXCLK)

◇rxd[7..0]--receiving data

◇rxdv--receiving data valid indication

◇rxer--receiving data error indication

◇col--Conflict Detection (only for half-duplex state)

Manage Configurations

◇mdc--Configuring Interface Clocks

◇mdio--Configuring interface I/O

The Management configuration interface controls the properties of the PHY. The interface has 32 register addresses, 16 bits per address. Of these, the first 16 have been specified in the "IEEE 802.3,2000-22.2.4management Functions", while the rest are designated by the individual devices themselves.

Mii/rmii is just an interface, for 10M wire speed, the MII rate is 2.5m,rmii 5M; for 100M wire speed, the MII rate is 25m,rmii 50M.

Sgmii--serial Gigabit Media Independentinterface

Sgmii is the interface between PHY and Mac, similar to Gmii and Rgmii, except that gmii and rgmii are parallel, and need to follow the clock, PCB cabling is relatively troublesome, and does not adapt to backplane applications.

While the SGMII is serial and does not need to provide additional clocks, both Mac and PHY require CDR to recover the clock. In addition, the SGMII is 8B/10B encoded at a rate of 1.25G.

Configuring PHY in Linux

Drivers/net/phy

The configured parameters are adaptive, 1000M, full duplex.

Phydev-> autonet, speed, duplex.

1. Mdio Introduction

The MDIO interface is a simple, two-wire, serial interface to connect a management entity and a managed PHY for the Purpos Es of controlling the PHY and gathering status from the PHY.
The lines include the MDC line [Management data Clock], and the "MDIO line [Management data input/output]. The clock is point-to-point and while the data line is a bi-directional Multi-drop interface.
The data line was tri-state able and can drive, devices.

Mdio interface, management interface between Mac and PHY (MII is Data interface), there are 2 lines: Clock line MDC, data cable Mdio (bidirectional)



Mdio Workflow:
* PREAMLE (PRE) The data cable mdio is in a high impedance state (always 1) when there is no idle state to transmit data.
* Start of Frame (ST) Mac drive Mdio line, a 2bit start identifier (01) appears.
* Operation Code (OP) Mac driver Mdio Line, a 2bit data is present to identify whether it is a read operation (10) or a write operation (01).
* PHY address (Phyad) Mac driver Mdio Line, the address of a 5bit data identification PHY is present.
* Reg address (Regad) Mac driver Mdio line, a 5bitPHY register addresses appear.
* Turnaround (TA) write operation, Mac drive Mdio line, appears 10
Read operation, MDIO pin of MAC must is put in high-impedance state
In the second cycle, the PHY drives the Mdio line, which appears 0

* Data Mdio Serial readout/writing of 16bit registers.

* Mdio reverts to idle state while Mdio enters high impedance state.


Here is an example of the PHY chip BCM5461:


2. PowerPC's support for Mdio

When PowerPC operates Mdio, the following registers are involved:
MIIMCFG Configuration Register
miimcom Command Register
Miimadd Address Register
Miimcon Control Register
Miimstat Status Register
Miimind Indication Register

For MPC8560 example, the positions of these registers in CCSR are as follows:






2.1 Miimcfg: Configuration register


RESETMGMT: For resetting the Mdio module
Mgmtclockset: Clock setting, is one of the 2 of the CCB's n-th party



2.2 miimcom Command Register


Readcycle:0->1 Trigger Mdio Read timing


2.3 Miimadd Address Register


Phyaddr:phy address, total 5bit, system up to 31 PHY (address 0 reserved)
REGADDR: Register address, Total 5bit, up to 32 register addresses on one PHY (can use shadow value technology to access more registers)


2.4 Miimcon Control Register



Phycontrol: The value to write to the register is stored here when the process is written


2.5 Miimstat Status Register



Phystatus: When the process is read, the contents of the PHY reg are placed here

2.6 Miimind Indication Register


Notval: If 1 is the end of the reading process, you can read the Miimstat
Scan: 1 Indicates the scanning process is in progress.
Busy: Only 0 o'clock for new reading and writing processes



3. Implementation of Mdio in Linux

2 functions when reading and writing PHY registers

Phy_read () and Phy_write (),

Final Call
int Gfar_local_mdio_read (struct gfar_mii *regs, int mii_id, int regnum)
int gfar_local_mdio_write (struct gfar_mii *regs, int mii_id, int regnum, U16 value)

The parameter regs is the Mdio related register:

1. struct Gfar_mii {
2. U32 miimcfg; /* 0x.520-mii Management Config Register */
3. U32 miimcom; /* 0x.524-mii Management Command Register */
4. U32 Miimadd; /* 0x.528-mii Management Address Register */
5. U32 Miimcon; /* 0x.52c-mii Management Control Register */
6. U32 Miimstat; /* 0x.530-mii Management Status Register */
7. U32 Miimind; /* 0x.534-mii Management Indicator Register */
8. };

Parameter mii_id, which is the PHY ID
Parameter Regnum, which is the register address


On the code, simple does not explain

2. int Gfar_local_mdio_read (struct gfar_mii *regs, int mii_id, int regnum)
6. {
8. U16 value;
12. /* Set The PHY address and the register address we want to read */
14. Gfar_write (&regs->miimadd, (mii_id << 8) | regnum);
18. /* Clear miimcom, and then initiate a read */
20. Gfar_write (&regs->miimcom, 0);
22. Gfar_write (&regs->miimcom, Mii_read_command);
26. /* Wait for the transaction to finish */
28. while (Gfar_read (&regs->miimind) & (Miimind_notvalid | MIIMIND_BUSY))
30. Cpu_relax ();
34. /* Grab The value of the register from Miimstat */
36. Value = Gfar_read (&regs->miimstat);
40. return value;
42. }

1. Int gfar_local_mdio_write (struct gfar_mii *regs, int  mii_id,
2.               int  regnum, u16 value)
3. {
4.     /* Set The PHY address and the register addres s we want to write */
5.     gfar_write (&regs->miimadd,  (mii_id <<& NBSP;8)  | regnum);
7.     /* Write out the value we want */
8.     gfar_write (&am P;regs->miimcon, value);
10.     /* Wait for the transaction to finish */
11. &NBSP;&NBSP;&NBSP;&NBSP;WHILE&N BSP; (Gfar_read (&regs->miimind)  & miimind_busy)
12.          cpu_relax ();
14.     return 0;
15. }

Preparation for kernel startup

4.1 Initialize network-related global data structures and mount hook functions that handle network-related soft interrupts
Start_kernel ()
-Rest_init ()
-Do_basic_setup ()
-Do_initcall
-->net_dev_init

__init Net_dev_init ()
{
Each CPU has a CPU private variable _get_cpu_var (softnet_data)
_get_cpu_var (softnet_data). Poll_list is important, the soft interrupt needs to traverse its
FOR_EACH_POSSIBLE_CPU (i) {
struct Softnet_data *queue;
Queue = &per_cpu (Softnet_data, i);
Skb_queue_head_init (&queue->input_pkt_queue);
Queue->completion_queue = NULL;
Init_list_head (&queue->poll_list);
Queue->backlog.poll = Process_backlog;
Queue->backlog.weight = weight_p;
}
OPEN_SOFTIRQ (NET_TX_SOFTIRQ, net_tx_action, NULL); Hang network send handler on soft interrupt
OPEN_SOFTIRQ (NET_RX_SOFTIRQ, net_rx_action, NULL); Hook up network receive handler on soft interrupt
}
4.2 Load the drive of a network device
Note: The network device here refers to the MAC layer of the network device, namely the TSEC and PCI network card (bcm5461 is PHY)
Create a Net_device data structure in the network device driver and initialize its hook function open (), close (), etc.
The entry function of the driver that mounts the TSEC is Gfar_probe

Data structure of platform device tsec
static struct Platform_driver Gfar_driver = {
. Probe = Gfar_probe,
. remove = Gfar_remove,
. Driver = {
. Name = "Fsl-gianfar",
},
};

int gfar_probe (struct platform_device *pdev)
{
dev = Alloc_etherdev (sizeof (*PRIV)); Creating Net_device Data Structures

Dev->open = Gfar_enet_open;
Dev->hard_start_xmit = Gfar_start_xmit;
Dev->tx_timeout = Gfar_timeout;
Dev->watchdog_timeo = Tx_timeout;
#ifdef CONFIG_GFAR_NAPI
Netif_napi_add (Dev, &priv->napi,gfar_poll,gfar_dev_weight); The poll hook function is called in the soft interrupt
#endif
#ifdef Config_net_poll_controller
Dev->poll_controller = Gfar_netpoll;
#endif
Dev->stop = Gfar_close;
DEV-&GT;CHANGE_MTU = GFAR_CHANGE_MTU;
DEV-&GT;MTU = 1500;
Dev->set_multicast_list = Gfar_set_multi;
dev->set_mac_address = gfar_set_mac_address;
Dev->ethtool_ops = &gfar_ethtool_ops;
}

V. Enabling network devices
5.1 The user calls the Ifconfig program and then enters the kernel via the IOCTL system call
The IOCTL () system Call of the socket
-Sock_ioctl ()
--DEV_IOCTL ()//Judge Siocsifflags
--__dev_get_by_name (NET, ifr->ifr_name)//select Net_device by name
--Dev_change_flags ()//Judge Iff_up
--Dev_open (Net_device)//Call the Open hook function

For tsec, the hook function to hang is Gfar_enet_open (net_device)

5.2 In the open hook function of the network device, assign receive BD, Hang interrupt ISR (including RX, TX, err), for tsec
Gfar_enet_open
--Assigning consistent DMA memory to the RX Tx Bd
--Assign the "EA address" of the RX BD to the data structure and assign the physical address to the TSEC register
--Assign the "EA address" of the TX BD to the data structure and assign the physical address to the TSEC register
--allocates memory to the Tx_skbuff pointer array and initializes it to null
--allocates memory to the Rx_skbuff pointer array and initializes it to null

--Initialization of TX Bd
--Initialize RX Bd, pre-allocate storage Ethernet packet SKB, using a one-time DMA mapping
(Note: #define DEFAULT_RX_BUFFER_SIZE 1536 ensures that the SKB can save an Ethernet packet)
RXBDP = priv->rx_bd_base;
for (i = 0; i < priv->rx_ring_size; i++) {
struct Sk_buff *skb = NULL;
Rxbdp->status = 0;
Here really assigns SKB, and initializes rxbpd->bufptr, Rxbdpd->length
SKB = Gfar_new_skb (dev, rxbdp);
Priv->rx_skbuff[i] = SKB;
rxbdp++;
}
rxbdp--;
Rxbdp->status |= Rxbd_wrap; Mark the wrap tag for the last BD setting

--register TSEC related interrupts handler: error, receive, send
REQUEST_IRQ (Priv->interrupterror, gfar_error, 0, "Enet_error", Dev)
REQUEST_IRQ (Priv->interrupttransmit, gfar_transmit, 0, "Enet_tx", dev)//packet sent out
REQUEST_IRQ (priv->interruptreceive, gfar_receive, 0, "Enet_rx", dev)//packet received

-->gfar_start (Net_device)
Enable RX, Tx
To turn on the tsec DMA register
Mask off the interrupt event that we don't care about

Finally, the tsec-related data structures such as BD should look like this

Six, interrupt in the receiving Ethernet packet

The Tsec Rx has been enabled, and the flow of network packets into memory is:
Network cable--RJ45---MDI differential line
--bcm5461 (PHY chip for digital-to-analog conversion)--Mii bus
--TSEC's DMA Engine automatically checks for the next available RX BD
DMA the network packet to the memory pointed to by the Rx BD, i.e. Skb->data

When a complete Ethernet packet is received, TSEC triggers a Rx external interrupt based on the event mask.
The CPU saves the scene, according to the interrupt vector, begins to execute the external interrupt processing function DO_IRQ ()

DO_IRQ Pseudo-code
{
Top half handles hard interrupts
View the interrupt source register to know that the network peripheral has generated an external interrupt
Rx Interrupt handler for performing network devices (different devices, different functions, but similar processes, tsec is gfar_receive)
1. Mask off the Rx event, and then the packet will not produce a RX interrupt
2. Add napi_state_sched status to Napi_struct.state
3. Hang the network device's own NAPI_STRUCT structure to the CPU private variable _get_cpu_var (softnet_data). poll_list
4. Trigger network receive soft interrupt
The lower half handles soft interrupts
Perform all soft interrupt handler in turn, including Timer,tasklet, etc.
Performing a soft interrupt for network reception handler Net_rx_action
1. Traverse the CPU Private variable _get_cpu_var (softnet_data). poll_list
2. Remove the napi_struct structure hanging above the poll_list, execute the hook function napi_struct.poll ()
(The device is different, the hook function is different, the process is similar, tsec is Gfar_poll)
3. If the poll hook function finishes processing all packages, the Rx event mask is turned on and the RX interrupt is generated when the packet is sent.
4. Call Napi_complete (napi_struct *n)
Remove the napi_struct structure from the _get_cpu_var (softnet_data). poll_list
and remove the napi_state_sched state of Napi_struct.state.
}

6.1 Tsec's receive interrupt handler function
Gfar_receive
{
#ifdef CONFIG_GFAR_NAPI
Test_and_set the current Net_device napi_struct.state is napi_state_sched
Calling Net_rx_action in a soft interrupt will check the status napi_struct.state
if (Netif_rx_schedule_prep (Dev, &priv->napi)) {
TempVal = Gfar_read (&priv->regs->imask);
TempVal &= imask_rx_disabled; Mask off Rx, no more RX interrupts
Gfar_write (&priv->regs->imask, tempval);
Hangs the napi_struct.poll_list of the current net_device to
CPU Private variable __get_cpu_var (softnet_data). Poll_list on and trigger soft interrupt
Therefore, when calling Net_rx_action in a soft interrupt, the current net_device is executed
Napi_struct.poll () hook function, i.e. gfar_poll ()
__netif_rx_schedule (Dev, &priv->napi);
}
#else
Gfar_clean_rx_ring (Dev, priv->rx_ring_size);
#endif
}

Http://tech.watchstor.com/storage-network-115062.htm

http://blog.csdn.net/jw212/article/details/6738457

12909341

----PHY Configuration of Linux network subsystem