20135316 King Cambridge Linux Fifth Week Lab notes

4.1.1 the visible state of the programmer

————

each instruction of the Y86 reads or modifies portions of the processor state , known as the programmer's visible state . as shown in 1 .

1. Program Registers:%eax,%ECX,%edx,%EBX,%esi,%edi,%esp and %ebp. It's all on the same level .

2. Condition Code (Condition codes): ZF ( 0 flag ), SF ( symbol sign ), of ( overflow flag) . Used to hold the effect of the most recent arithmetic or logical instruction .

3. Program Counter (PC): stores the address currently being executed .

4. Memory : in the programmer's opinion , the Y86 program uses virtual memory .

5. Status Code (state): indicates the overall state of the program execution , which indicates normal operation , or an exception occurred .

4.1.2 Instruction Set

————

Figure 2 is a simple description of the Y86 instruction set . similar to IA32 's/t instruction set .  The data for the operation is 4 bytes . instruction encoding length 1-6 bytes .

The format of the instruction is probably : Icode:ifun ra:rb D, as shown in the following:

Instruction classification	Specific instructions	Description
Delivery Instructions (XXMOVL) (4 types )	Instructions Source Objective Irmovl Immediate number Register Rrmovl Register Register Mrmovl Memory Register Rmmovl Register Memory	the Y86 instruction is addressed in a single way : base + offset .
Arithmetic logic directive (OPL) (4 )	Addl, Subl, Andl, Xorl	The execution of these 4 instructions sets the condition code (CC).
Jump instruction (JXX) (4 )	JMP, Jle, JL, je, jne, Jge, JG	JMP is an unconditional jump instruction , the other is conditional jump instruction ( Select a branch based on the criteria code ).
Conditional delivery instruction (CMOVXX) (6 )	Cmovle, CMOVL, Cmove, Cmovne, Cmovge, CMOVG	Select whether to update the destination register according to the criteria code .
Call/ret Directive	Call/ret	Call will return the address into the stack and the destination address . The RET instruction is returned from the procedure call .
PUSHL/POPL Directive	Pushl/popl	into the stack and out of the stack operation .
Halt Directive	Halt	Stops execution of instruction directives . Set the Stat bit HLT.
NOP Instructions	Nop

4.1.3 Instruction Set encoding

————

Y86 instruction 1-6 bytes . The first byte indicates the type of instruction , where the high 4 bits are the code part , and the lower 4 bits are function codes (functions). the code value of Y86 is 0~0xb.

Figure 3 shows the integer operation , conditional delivery and the specific encoding of the conditional delivery instruction (the first byte ), the function code of the other instruction is 0 ( can be extended ).

Register encoding

——

For convenience , each program register uses 4 -bit encoding , where F indicates no register .

4.1.4 Status Codes and exceptions

————

A status Code (Stat) is one of the visible states of a programmer that describes the overall state of a program's execution . See Figure 5.

An applicable processor , when the processor encounters an exception, invokes an exception handler . In Y86, When an exception is encountered , direct the processor to stop executing the instruction .

4.2 Logic Design and Hardware control Language HCL

The implementation of a digital system requires three main components:combinational logic of bit arithmetic functions, memory elements, clock signals。

The syntax of VHDL is similar to the ADA language, while the Verilog HDL syntax is similar to the C language.

4.2.2 Combination Circuit and HCl Boolean expression

The composition of the combined circuit has two limits:

1). The output of multiple logic gates cannot be joined together, otherwise it will cause the contradiction of the input signal.
2). Must be non-ring.

4.2.3-character combination circuit and HCl integer expression

The Arithmetic/logic unit (ALU) is a very important combination circuit.

4.2.5 memory and clock control

The combinational circuit essentially does not store any information, but simply responds to the input signal and produces a function output. In order to produce a sequential circuit-that is, a system with a state and a state-based calculation, a device that stores information on a bitwise basis must be introduced.

Two types of storage devices:

Clock registers: storing single words
Random access Memory: Store multiple words, with address selection. Examples include the virtual memory system, the register heap, and here, the Register identifier (ID) as the address.

In hardware and machine-level programming, the meaning of "registers" is slightly different. In hardware, registers directly connect their input and output lines to other parts of the circuit. In machine-level programming, registers represent a small number of addressable words in the CPU, where the address is the register ID. Respectively, these two types of registers are hardware registers and program registers.

sequential implementation of 4.3 Y86

4.3.1 will process the organization into stages

Take a finger (fetch)

The value phase reads the instruction byte from the memory and puts it into the instruction memory (CPU), and the address is the value of the program counter (PC).

It computes the address of the next instruction in the current instruction in a sequential manner (that is, the value of the PC plus the length of the removed instruction)

Decoding (decode)

The ALU reads up to two operands from a register file (a collection of universal registers). (which reads up to two registers at a time)

Execute (EXECUTE)

The Arithmetic/logic unit (ALU) is used for different purposes in the execution phase, depending on the type of instruction. For other instructions, it will be counted as an adder to add or decrease the stack pointer, or to calculate a valid address, or simply add 0 to pass an input to the output.

The Condition Code Register (CC) has three condition bits. The ALU is responsible for calculating the new value of the condition code. When a jump instruction is executed, the branch signal CND is calculated based on the condition code and the jump type.

Visit (Memory)

A memory word is read or written to the data memory (CPU) during the visit. The instruction and data memory accesses the same memory location, but is used for different purposes.

Writeback (write back)

Write-back stage can write up to two results to the register file. The register file has two write ports. Port e is used to write values computed by the ALU, and Port m is used to write values read from the data memory.

Update PC (PC update)

Based on the instruction code and the branch flag, the value of the next PC is selected in the signal values from the previous steps.

We use the SEQ (sequential sequential) processor as an example to explain the fundamentals of the CPU. On each clock cycle, SEQ executes all the steps required to process a complete instruction. However, this requires a very long clock cycle time, so the clock cycle frequency is low to unacceptable.

Timing of SEQ

Combinatorial Logic no timing or control is required-as long as the input changes , the value is propagated through the logical gate network.

We also look at random access memory (register file, instruction memory, and data memory) as a combination of logical operations. ( write random access memory needs to wait for high level)

Since instruction memory is used only for reading instructions, we can consider this unit as a combinatorial logic. (The write instruction in memory to instruction memory is that events outside the CPU are not part of the CPU timing)

Each clock cycle, the program counter will load the new instruction address.

The condition code register is loaded only when an integer operation instruction is executed.

The data memory is only written when the MOV, push, and call instructions are executed.

to control the timing of the active in the processor, only the clock control of registers and memory is required .

Because the instruction runs the result of the calculation, it is written to the register or memory.

We can consider the process of reference, decoding, and execution as a process of combinatorial logic (since they do not involve write registers). Think of writeback as another process.

The entire process can be simplified to the following:

Problems encountered in learning:

1. The first is unfamiliar with the instructions, some address changes are not very clear, the code of the instruction is now to rely on the form of the book to do so. In the future to practice more, to increase familiarity.

2. The order of Y86 to achieve only abstract understanding, read the book after the feeling is very chaotic, too many things to remember, there is not too much real understanding, the concept of things too much, through experimental operation better understanding of the use.

20135316 King Cambridge Linux Fifth Week Lab notes