components of the Makefile
Makefile contains five things: display rules, implicit rules, variable definitions, file indications, annotations. specific meaning or direct reference to the online version of it | | |
1, explicit rules. Explicit rules explain how to generate one or more target files. This is clearly indicated by the writer of the Makefile , to generate the file, the file 's dependent file, the generated command.
2, implicit rules. Since our make has the function of automatic derivation, the obscure rules allow us to write Makefilein a rough manner, which is made Supported by the.
3, the definition of variables. In Makefile We want to define a series of variables, the variables are generally strings, this is a bit of your C language macro, when Makefile when executed, the variables are extended to the corresponding reference position.
4, the document instruction. It consists of three parts, one referring to another Makefilein one Makefile, like the C language Include , and the other is to specify a valid part of Makefile based on certain circumstances , just like A precompiled # in C If the same is true, there is a command that defines a multiline. I'll tell you about this part of the story in the next section.
5, comments. There are only line comments in Makefile, like UNIX Shell scripts, whose comments are "#" character, this is like C + + in the "//" The same. If you want to use the "#" character in your Makefile , you can escape it with a backslash, such as"/#".
Finally, it is worth mentioning that the the command in Makefile must start with the [Tab] key.
here , the rules. (Rules) :
Target ...: Prerequisites ...
Command
...
...
A rule consists of three parts, a target, aprerequisite (Prerequisites), and a command (commands).
Target is a destination file , which can be either an objector an executable file. It can also be a label.
Prerequisites is to generate the desired file or target for that target.
command is what the make needs to execute. (arbitrary Shell command)
This is a file dependency, meaningthat one or more target files depend on the files in the prerequisites, and their generation rules are defined in the command the.
White Point isthat prerequisites if there is more than one file to be newer than the target file,command The defined command is executed.
this is Makefile 's rules. This is the core content of Makefile.
The core idea of Makefile
four characters, dependency
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