Address mapping of Linux memory management

Write in front: Because address mapping involves setting access to various registers, Linux has different methods for addressing different architecture processors, for example, for I386 and later 32-bit Intel processors using a 2-level page table map in page-map. For IA64 processors, 3 levels of paging are used. For other types of processors, such as MK68000 and many other processors, the segment mapping is ignored when addressing mapping, only because Intel's X86 series needs to be compatible with earlier segment mappings, which is used in later designs as segment mapping and page-based mapping. Later notes on Linux, in addition to special instructions, are on the i386 architecture, all the source code in the notes except special instructions are taken from the linux-2.4.0 source tree.

Modern operating systems use efficient page management in memory management, and Linux is no exception. There are some exceptions to the I386 processor, which, in order to be compatible with earlier processors, requires that the segment mapping be preceded by Intel. At address mapping, the virtual address is divided into a fixed page size, and the MMU maps the virtual address to the actual physical address. In the memory space represented by the access to a virtual address, the CPU must undergo several memory accesses to complete the mapping, with the number of accesses N+1 (n being the page table series) and n addition operations.

Before Linux can segment-map and page-map, you need to understand how the X86 series addresses are described:

• Logical address: The address that appears in the machine instruction used to make the operand.
• Linear address: A logical address is given a linear address after being processed by a segmented unit, which is a 32-bit unsigned integer that can be used to locate 4G of storage units.
• Physical Address: The linear address is found after the page table to obtain the physical address, this address will be sent to the address bus to indicate the physical internal deposit to be accessed.

A segment mapping is a mapping of a logical address to a linear address, whereas a page map corresponds to a linear address and a physical address. Segment mapping phase: I386CPU selects the current value of the code segment Register CS as the subscript in the Segment Descriptor table, the 2nd bit of the segment register is 0 when GDT is used, and the LDT is used at 1. Intel is designed to use GDT for the kernel, each process uses its own LDT, and the lowest two bits of the register represent the privilege level. In fact, only the GDT is used in the Linux kernel, only 0 for the kernel level in 4 permission levels, and 3 for the user level. The kernel sets its segment register when a new process is created, and the set code for the segment register in the I386 processor is located in the Include/asm-i386/processor.h

Include/asm-i386/processor.h #define Start_thread (regs, New_eip, New_esp) do {       __asm__ ("Movl%0,%%fs; MOVL%0,%%gs "::" R "(0));    Set_fs (user_ds);                    Regs->xds = __user_ds;                   Regs->xes = __user_ds;                   REGS->XSS = __user_ds;                   Regs->xcs = __user_cs;                   Regs->eip = New_eip;                 Regs->esp = New_esp;             } while (0)

As can be seen from the code, Linux sets the DS,ES,SS register of the I386 processor to User_ds, which means that the data segment and the stack segment are indistinguishable from the code snippet for the process in Linux. The settings for __user_cs and __user_ds are located in Include/asm-i386/segment.h

Include/asm-i386/segment.h #ifndef _asm_segment_h#define _asm_segment_h  #define __KERNEL_CS 0x10#define __KERNEL _ds 0x18  #define __USER_CS   0x23#define __user_ds   0x2B  #endif

From the above code can be seen, the content of CS Register is 0x23, through the meaning of the paragraph register everyone, the CPU with 4 as subscript, from the global Descriptor list GDT looking for paragraph description options, GDT content in Arch/i386/kernel/head. Defined in S

arch/i386/kernel/head. S ENTRY (gdt_table). Quad 0x0000000000000000/* NULL descriptor */. Quad 0x0000000000000000/* not used */.  Quad 0X00CF9A000000FFFF/* 0x10 kernel 4GB Code at 0X00000000 */. Quad 0X00CF92000000FFFF/* 0x18 kernel 4GB data At 0x00000000 */. Quad 0X00CFFA000000FFFF/* 0x23 user 4GB Code at 0x00000000 */. Quad 0X00CFF2000000FFFF/ * 0X2B user 4GB data at 0x00000000 */. Quad 0x0000000000000000/* not used */. Quad 0x0000000000000000/* No     T used */* * The APM segments has a byte granularity and their bases * and limits is set at run time. */. Quad 0x0040920000000000/* 0x40 APM set up for Bad BIOS's */. Quad 0x00409a0000000000/* 0x48 APM CS Co De * */. Quad 0x00009a0000000000/* 0x50 APM CS-code (+) */. Quad 0x0040920000000000/* 0x58 APM DS D ATA */. Fill nr_cpus*4,8,0/* Space for TSS ' s and LDT ' s */

To this segment mapping has been completed, in fact, for the page-map of Linux, this step is completely useless but have to do. With segment mapping, the logical address of a process is mapped to a linear address, but in fact the meaning of the segment descriptor is the same.   Page-map phase: In page storage, each process has its own PGD, pointer to PGD exists in the mm_struct of the process, each time the process runs, the kernel needs to set the control register Cr3,mmu is to get the page directory pointer from CR3. We know that the CPU is using the virtual address when executing the program, while the MMU hardware uses the actual physical memory address when mapping, its implementation is implemented by the function in Include/asm-i386/mmu_context.h

include/asm-i386/mmu_context.h static inline void switch_mm (struct mm_struct *prev, struct mm_struct *next, struct task_s Truct *tsk, unsigned CPU) {if (prev! = next) {/* Stop flush IPIs for the previous mm */Clear_bit (CPU, &        Amp;prev->cpu_vm_mask);            /* * Re-load LDT if necessary */if (prev->context.segments! = next->context.segments)        Load_ldt (Next), #ifdef config_smp cpu_tlbstate[cpu].state = TLBSTATE_OK;        cpu_tlbstate[cpu].active_mm = Next; #endif set_bit (CPU, &next->cpu_vm_mask);    /* Re-load page Tables */ASM volatile ("Movl%0,%%CR3":: "R" (__pa (NEXT->PGD)));        } #ifdef CONFIG_SMP else {cpu_tlbstate[cpu].state = TLBSTATE_OK;        if (cpu_tlbstate[cpu].active_mm! = Next) BUG ();              if (!test_and_set_bit (CPU, &next->cpu_vm_mask)) {/* We were in lazy tlb mode and leave_mm disabled * TLB Flush IPI delivery. We Must flush OUR tlb.        */local_flush_tlb (); }} #endif} #define ACTIVATE_MM (prev, next) switch_mm ((prev), (next), null,smp_processor_id ()) #endif

Focus on the ASM volatile ("Movl%0,%%CR3":: "R" (__pa (NEXT->PGD))), which is implemented to read the page directory pointer into the CR3 register. The highest 10 bits of the linear address can be known from the page directory of the specific directory entry, after the directory entry of the process is found, in the directory entry, the high 20 bits to the page table, after the page table, the CPU from the middle of the linear address 10 bits to get the table entries in the page table. The high 20 bits in the page table on the 32-bit processor point to the initial address of the physical memory, add 12 0 after that, and then include the low 12 bits in the linear address (that is, the offset in the linear address), so that a specific physical address is obtained.

On the issue of address mapping, the kernel only provides page tables, and the actual conversion is done by hardware. So how does the kernel generate these page tables? This has two aspects of content, virtual address space management and physical memory management. In fact, only the user-State address mapping needs to be managed, the kernel-State address mapping is written to [0xc000 0000] (3 GB) to [0xFFFF FFFF] (4 GB). In this section, one of the key functions that the kernel implements is to improve the speed of lookups through caching.

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Address mapping of Linux memory management