< turn >nios II embedded System hardware design (I.)

Original address: Http://bbs.ednchina.com/BLOG_ARTICLE_182065.HTM

SDRAM Controller parameter Settings

Sopc through the SDRAM controller and the SDRAM on the board to communicate, in the sopc to add SDRAM Controllers, the following dialog box, the specific parameters described below.

First, Memory Profile parameter Settings

Presets : In this drop-down menu, some common SDRAM parameters are preset, and the corresponding settings are automatically modified after the SDRAM of a certain model is selected. The preset SDRAM signals are:

Micron MT8LSDT1664HG Module

Four SDR100 8 MBytex16 chips

Single Micron mt48lc2m32b2-7 chip

Single Micron mt48lc4m32b2-7 chip

Single NEC D4564163-A80 chip (MBytex16)

Single Alliance as4lc1m16s1-10 chip

Single Alliance as4lc2m8s0-10 chip

Data width: bit width.

Chip selects: Chips pick-up signal.

Banks: Sets the number of banks of the DRAM chip.

Because of technology, cost and other reasons, SDRAM is generally not made into a single storage array, but the SDRAM internal division into several banks. It was two earlier and is now basically four. So in addressing is the first to determine at which bank, then select the row and column address in the bank.

Row: Sets the number of line address lines.

Column: Sets the number of column address lines.

Line Address line and column address line and greater than the total address line, this is because the address line is multiplexed, in the read and write operation, the first send off the address, and then send the column address, there is Ras,cas control.

Share pins via TriState bridge: After the controller shares dq/dqm/addr I/O pins is selected, the DQ/DQM/ADDR pin can be reused with other devices on the tri-state bus specified below.

Second, Timing parameter Settings

CAS Latency Cycles

After the CAS is issued, it still takes a certain amount of time to have the data output, from the time the CAs and the read command are emitted to the first data output, are defined as CL (CAS latency,cas incubation period). CL is also known as the Read latency (Rl,read Latency) because CL is only present when it is read. The unit of CL is usually the number of clock cycles, which is determined by the clock frequency.

Initialization Refresh Cycles

The refresh period that is required during initialization.

Isssue One Refresh command every

Refresh cycle.

DRAM, known as DRAM, is one of the most important operations of DRAM because it is constantly refreshed (refresh) to hold data. The refresh operation is usually read and then written with S-amp. So how often do you repeat a refresh? It is now accepted that the maximum data retention period for a capacitor in a storage body is 64ms (milliseconds, 1/1000 seconds), which means that the cycle time for each row refresh is 64ms. So the refresh speed is: The number of rows/64ms. When we look at the memory specifications, we often see the 4096 refresh Cycles/64ms or 8192 refresh cycles/64ms, where 4096 and 8192 represent the number of rows per L-bank in the chip. The refresh command is valid for one row at a time, and the send interval varies with the total number of rows, with 4096 rows of 15.625μs (microseconds, 1/1000 milliseconds) and 8192 rows as 7.8125μs.

There are two types of refresh operations: Automatic refresh (auto refresh, or AR) and self refresh (auto refresh, referred to as SR). Regardless of the Refresh method, you do not need to provide the row address information externally, because this is an internal automatic operation.

For AR, there is a line address generator (also called a refresh counter) inside the SDRAM that is used to automatically generate the line address sequentially. Because the refresh is for all the storage in a row, no column addressing is required, or CAS is valid before RAS. Therefore, AR is also known as CBR (CAS before RAS, column ahead of row positioning) type refresh. Since the refresh involves all L-bank, all l-bank stop working during the refresh process, and each refresh takes up to 9 clock cycles (PC133 standard), which can then enter a normal working state, meaning that all work orders can only wait for the 9 clock period to be executed. After 64ms, the same row is refreshed again, so the cycle is refreshed. Obviously, the refresh operation will certainly have an impact on the performance of SDRAM, but this is not a way to do, but also dram relative to SRAM (static memory, no need to refresh still can retain data) cost advantages of the costs.

SR is mainly used in the sleep mode low-power state of the data preservation, this time no longer rely on the system clock operation, but based on the internal clock to refresh. All external signals except CKE during the SR are not valid (no external refresh instructions required), and only re-enable the Cke to exit from refresh mode and enter normal operation state.

Delay after PowerUp before initialization

The stable period after power-up. Generally given in the manual is 200us, usually we choose 100us . after power-up there is an initial project, the timing is as follows:

Duration of Refresh Command

The duration of each refresh. It is usually 70nsor more. For each refresh mentioned above, the elapsed time is 9 clock cycles (PC133 Standard), then 9/133mhz=67.7ns.

Duration of Prechange command

Pre-charge cycle. After a pre-charge command is issued, it takes a while to allow a valid command to send a RAS line to open a new work line, which is called TRP (precharge command Period, pre-charge active period). TRP units are generally also the number of clock cycles, depending on the clock frequency depends on the value. The ezniosdk user can choose 20ns.

In fact, pre-charging is a data rewrite of all the storage in the work line, and the line address is reset, while releasing the inside of the chip comparator (re-added to the comparator voltage , usually the capacitor voltage to help determine the logic level of reading data), To prepare a new line of work. Specifically, the data in the amplifier / Drive Comparator is written back. The capacitance capacity in the storage unit is small, and even the non-working storage will be disturbed by the row-by-line, so it needs to be rewritten after reading.

ACTIVE to READ or WRITE delay

    When sending a column read-write command, there must be an interval between the row-valid command and the interval defined asTRCD, i.e.RAS to CAS Delay（RASToCASDelay), can also be understood as the line-in cycle, which should be based on the chip storage array of electronic components response time (from one state to another state change process) of the delay.TRCDIsSDRAMOne of the important timing parameters. Broad-senseTRCDIn Clock cycles (TCK，Clock TimeNumber of units, such astrcd=2, which represents a delay period of two clock cycles, specific to the exact time, depends on the clock frequency, for running in the100MOfSDRAM，trcd= "2"Represent20nsThe delay, forPC133is the15ns。

Access time

Access time.

I/O a clock rising edge before the data output on the bus, the data is transmitted to the readout amplifier, that is, the data has been triggered, after a certain driving time eventually transmitted to the data i/o bus output, which we call tac (access Time from CLK , after which the clock is triggered. tac is in ns , the different frequencies have different explicit provisions, but must be less than one clock cycle, otherwise it will be too long to reduce the efficiency of access. For example pc133 has a clock cycle of 7.5ns , tac The is 5.4ns . It should be emphasized that each data is read with tac , which is included in the continuous read, is only the first data transfer, while the second one begins the Span style= "font-family: ' Times New Roman ';" >tac .

Write Recover Time

Write-back delay.

Although the write operation is 0 deferred, the true write of each data requires a sufficient period to ensure that this time is the writeback period (TWR). Therefore, pre-charging cannot be performed at the same time as the write operation, the pre-charging command must be issued after TWR to ensure reliable data writing, otherwise the rewritten data may be wrong, which results in a write-back delay.

< turn >nios II embedded System hardware design (I.)