Analysis of Linux memory layout based on mini2440

SDRAM (Synchronous dynamic random Access memory, synchronous RAM) is usually called memory. The working principle of memory, control timing, and the configuration method of related controller have been a difficult point in the process of embedded system learning and development. We analyze its principle from the angle of its hardware, and then draw out the driver writing process of SDRAM.

Memory is the code of execution space, take the PC as an example, the program is stored in the form of a file in the hard disk, the program is loaded into memory by the operating system before running, because the memory is RAM (random access memory), you can address to locate a byte of data, When the CPU executes the program, the value of the PC is set to the start address of the program in the memory, the CPU will be taken in sequence, decoding, executing, before the memory is initialized, memory is like a house that is not built, is unable to read and store the data, So we need to initialize the memory in order for MTOs to run in memory.

Universal Storage Devices:

Before describing how the memory works, it is important to understand how the storage device is stored: Rom,ram

L ROM(read-only memory): read-only memory is a solid-state semiconductor memory that can read only the data previously stored. The feature is that once the data is stored, it can no longer be changed or deleted. It is usually used in electronic or computer systems that do not require frequent changes to the data and will not disappear due to power off. such as: The BIOS inside the PC.

L RAM (Random access memory): Random access memory, the contents of the storage unit can be arbitrarily removed or deposited on demand, and the speed of access to the storage unit location independent of the memory. It can be understood that when you give a random, valid access address, RAM returns its stored content (random addressing), and its access speed is independent of the address. This kind of memory loses its storage content during power loss, so it is mainly used to store the program which is used randomly in short time. The memory address in a computer system is a four-byte aligned address (32-bit machine), CPU fetch, execution, storage is through the address, so it can be used to do memory.

RAM According to hardware design, random memory is also divided into dram (dynamic RAM) and SRAM (static RAM) random memory.

L DRAM: Its basic original is a small capacitor, the capacitor can be on two plates for a short period of time to retain the charge, can be through the polarity between the voltage difference between 0 and 1 of the computer, due to the physical characteristics of the capacitance, to regularly charge for it, otherwise the data will be lost. The charging process of the capacitor is called refresh, but the production process is simple, small size, easy to integrate, often as a computer memory to make the original. For example: The memory of the PC, SDRAM, DDR, DDR2, DDR3, etc., disadvantage: Due to periodically refresh the storage media, access speed is slow.

L SRAM: It is a kind of memory with still access function, it can save the data stored in it without needing to refresh the circuit. Therefore, its access speed is fast, but large size, power consumption, high cost, commonly used for storage capacity is not high, but fast access, such as the CPU L1 Cache,l2cache (first level, level two cache), register.

To meet the needs of development, MINI2440 three storage media at the factory:

(1) NOR FLASH (2M): ROM memory, usually used to save bootloader, boot system boot

(2) NAND FLASH (256M, different model, Nandflash size): Save operating system image file and file system

(3) SDRAM (64M): Memory, execution program

L NOR FLASH: It is characterized by support for XIP in-chip execution (execute in place) so that the application can run directly in Flash flash memory without having to read the code into the system RAM, which means it can be randomly addressed. NOR Flash costs higher.

L NAND FLASH: It provides very high cell density, high storage density, and fast write and erase speeds. The cost is low and XIP is not supported. Can be used in embedded data storage media. such as: Mobile phone memory card, SD card and so on.

1.1.1 s3c2440 memory address segment (Bank)

s3c2440 External led to 27 address line addr0~addr26, which can be addressed up to 128MB, and s3c2440 address space can reach 1GB, this is because s3c2440 will be 1GB of addressing space into 8 banks (BANK0~BANK7), Each bank corresponds to a chip selection signal line NGCS0~NGCS7, when accessing bankx, NGCSX pin level pull low, used to select the foreign connection device, s3c2440 through 8 signal lines and 27 address lines, you can access 1GB. As shown in 2-48.

Figure 2-48 s3c2440 Memory Bank

, the diagram on the left corresponds to not using Nandflash boot (via jumper settings), memory bank map, usually in this mode of boot selection norflash start, will norflash welding in Bank0, the system power, The CPU begins to fetch the finger from the start address of Bank0.

On the right is the option to boot from Nandflash (via jumper settings), after the system is power up, the CPU will automatically copy the Nandflash 4K data into the s3c2440 inside a 4K size SRAM type memory (called Steppingstone), Then take the finger from steppingstone to start.

Wherein BANK0~BANK5 can be welded ROM or SRAM type memory, BANK6~BANK7 can weld rom,sram,sdram type memory, that is, s3c2440 SDRAM memory should be welded on the BANK6~BANK7, The maximum supported memory 256m,bank0~bank5 is usually welded to boot the system to boot the small capacity ROM, specifically welding what kind of memory, how much capacity, according to each development board manufacturer different, such as the MINI2440 board will be 2 m norflash welding on the Bank0 , for storing the system boot program bootloader, the two 32m,16bit bit width SDRAM memory is soldered on Bank6 and Bank7, and the 64m,32 bit memory is formed in parallel.

Since the s3c2440 is a 32-bit chip, it is theoretically possible to reach the 4GB addressing range, removing the 8 banks used to connect external devices, and a portion of the address space is used for device special function registers, the remaining addresses are not used.

Table 2-14 s3c2440 Device Register address space

External devices	Start Address	End Address
Storage Controller	0x48000000	0x48000030
USB Host Controller	0x49000000	0x49000058
Interrupt Controller	0x4a000000	0x4a00001c
Dma	0x4b000000	0x4b0000e0
Clock and power management	0x4c000000	0x4c000014
LCD Controller	0x4d000000	0x4d000060
NAND Flash Controller	0x4e000000	0x4e000014
Camera interface	0x4f000000	0x4f0000a0
Uart	0x50000000	0x50008028
Pulse Width Modulation timer	0x51000000	0x51000040
USB Device	0x52000140	0x5200026f
Watchdog timer	0x53000000	0x53000008
IIC Controller	0x54000000	0x5400000c
IIS Controller	0x55000000	0x55000012
I/O port	0x56000000	0x560000b0
Real-Time Clock RTC	0x57000040	0x5700008b
A/D converters	0x58000000	0x58000010
Tp.	0x59000000	0x59000034
SD interface	0x5a000000	0x5a000040
AC97 Audio Coding Interface	0x5b000000	0x5b00001c

1.1.2 SDRAM Memory Operating principle

The internal SDRAM is a storage array. The array, like a table, "fills in" the data. In the same way that data is read and written, a row is specified, a column is specified, and we can find exactly what cells are needed, which is the basic principle of memory chip addressing, as shown in 2-49.

Figure 2-49 Memory line, column address addressing

This cell (storage array) is called the Logical Bank (Logical Bank, hereinafter referred to as L-bank). Due to technical, cost and other reasons, it is impossible to do only a full-capacity l-bank, and most importantly, due to the operating principle of SDRAM, a single l-ban k will cause very serious addressing conflicts, greatly reducing memory efficiency. So people in the SDRAM internal division into multiple L-bank, is basically 4 (this is also the maximum number of L-bank in the SDRAM specification), it can be seen that in addressing the first to determine which L-bank, and then in this selected L-bank select the corresponding row and column to address. So access to memory can only be a l-bank job at a time. 2-50:

Figure 2-50 Memory storage unit

When operating on memory (see), first determine the operation L-bank, so you want to select L-bank. The external pins on the memory chip have more than two pins BA0, BA1, used to select 4 L-bank. As mentioned earlier, the 32-bit address length is divided into a row address and a column address due to its storage structure characteristics. The following memory structure diagram shows that the memory socket address line only 13 address line a0~a12, it can only addressable 8 m of memory space, in the end what mechanism to implement the 64M memory space for addressing it? SDRAM line address line and column address line is time-sharing, that is, the address to be sent out twice, first send the travel address (Nsras line effective operation), and then send the address (Nscas column effective operation). This can greatly reduce the number of address lines, improve the performance of the device and the production process complexity. However, the addressing process can also become complex. In fact, the current SDRAM generally use L-bank as the basic addressing object. By L-bank Address line ban control the choice between L-bank, line address line and column address line through the connection of all L-bank, each L-bank the width of the data and the entire memory of the same width, so that the data can be stored faster. At the same time, ban can also enable the L-bank to operate in low-power mode, thereby reducing the power consumption of the device.

Figure 2-51 HY57561620 Internal structure diagram

Development Board Memory controller PIN wiring (take MINI2440 Development Board as an example):

(1) Determine the wiring of BA0 and BA1

Table 2-15 BA0, BA1 wiring

Bank size: External memory capacity size (HY57561620 is 4MBIT*16BIT*4BANK*2CHIPS/8=64MB)

Bus width: Two-piece 16-bit HY57561620, parallel to 32-bit
Base Component: Single chip Capacity (bit) (256MB)
Memory Configration: Ram configuration ((4m*16*4banks) *2chips)

By the Hardware manual bank address PIN Connection Configuration table, the use of a[25:24] two address line as the bank chip selection signal, just two wires can be selected each storage unit 4 banks.

(2) Determine other wiring

SDRAM memory is welded on the BANK6~BANK7, its welded pin, 2-52:

Figure 2-52 s3c2440 16-bit wide memory chip

Is s3c2440 provides two pieces of 16-bit chip parallel connection, an is the CPU address bus, wherein the A2~A14 is the memory chip addressing the bus, the address addressing bus starts from A2 because the memory address is byte-aligned, A24,A25 for L-bank chip selection signal, The DN is the CPU data bus, the other is the corresponding control signal line.

Table 2-16 memory chip each PIN description

External takeover pin Name	Internal takeover pin Name	Full Name	Describe
A2~a14	A0~a12	Address	Address line
D0 ~d31	Dq0~dq31	Data Input/output	Data cable
A24,a25	Ba0,ba1	Bank Address	L-bank Chip Selection Signal
Dqm0~dqm3	LDQM, UDQM	Data Input/output Mask	High, low-byte data mask signal
SCKE	SCKE	Clock Enable	Input clock active signal
SCLK	SCLK	Clock	Input clock
NSCS0	NSCS	General Chip Select	Chip selection signal (it is two functions of the same pin as the nGCS6)
Nsras	Nsras	Row Address Strobe	Line Address Select communication number
Nscas	Nscas	Column Address Strobe	Column Address Select communication number
Nwe	Newnwe	Write Enable	Write a valid signal

We can see through the s3c2440 16-bit wide memory chip wiring diagram, the two memory chips only two different places, LDQM, UDQM and the data bus dqn wiring method is not the same.

Since the memory chip has a bit width of 16 bits, it can be read two bytes at a time. However, typically the minimum addressing unit in the operating system is 1 bytes, so the memory controller must be guaranteed access to every byte of memory. UDQM,LDQM represents a high, low-byte read signal for 16-bit data, and when reading data, LDQM/UDQM is used to control whether the high-low byte in the 16-bit data can be read, when the LDQM/UDQM is low, the corresponding height/low byte can be read, if LDQM/ When the UDQM is high, the corresponding high/low byte cannot be read. When the data is written to the memory, the LDQM/UDQM control data can be written, when the LDQM/UDQM is low, the corresponding high/low byte is written, if the LDQM/UDQM is high, the corresponding high/low byte cannot be written. Through the control of the LDQM/UDQM signal can be controlled to two memory chip storage data, because two memory cell address line is universal, they can receive the address signal from the CPU, but to two storage units of the LDQM/UDQM signal is different, in order to distinguish the high and low byte of a word.

S3C2440A is a 32-bit CPU, that is, its data bus and address bus width is 32 bits (can be understood as 32 wire one end connected to the CPU, the other end connected to the memory controller), then the input/output of the memory data is also guaranteed to be 32-bit bus, The MINI2440 uses two 16-bit wide bus memory chips in parallel to form a 32-bit bus. One of the chips is connected to the low 16 bits of the CPU data bus, the other chip is connected to a high 16-bit on the data bus, and in parallel to the 32-bit bus, so the input/output bus of two chips is connected to different pins on the CPU bus.

Read operation of 1.1.3 SDRAM

SDRAM to read operations, the address line is sent to the address to read the data, through the knowledge of the previous, the address is divided into 3 parts, line address, column address, L-bank chip selection signal. The chip selection (L-bank) operation and the efficient operation of the line can be done at the same time.

At the same time as CS and L-bank are addressed, RAS (Nsras line address Select communication number) is also in a valid state. At this point an address line sends a specific line address. A0~a12, a total of 13 address lines (can represent 8192 lines), A0~a12 different values to determine the specific line address. Because the row is valid and the corresponding L-bank is valid, the line is valid and can also be called L-bank valid.

Once the line address is determined, the column address is addressed. However, the address line is still the a0~a12 used for the line address. Yes, in SDRAM, the row and column address lines are reused. The column addresses are multiplexed with A0~A8, a total of 9 (which can represent 512 columns). So, how does the read/write command come out? In fact, no signal is sent to read or write the explicit command, but through the chip's writable state control to achieve the purpose of reading/writing. Obviously we signal (NWE) is a key. When we are invalid, of course it is the Read command. When it is valid, it is to write commands.

SDRAM basic Operation command, through a combination of various control/address signals (h for high level, l for low level, X for high, low power average has no effect). In this table, all commands are the default cke (Sckel input clock frequency is valid) in addition to the self-refresh command. Both the column addressing signal and the read-write command are issued simultaneously. Although the address line is shared with row addressing, the CAS (Nscas column address select communication number) signal can differentiate between open and column addressing, with A0~A8,A9~A11 to determine the specific column address.

The read command is emitted with the column address (when we are low is the write command) However, in the Send column read and write command must have an interval with the row valid command, this interval is defined as TRCD, that is, RAS to CAS delay (RAS to CAS latency), this is very well understood, After the address line to send the line address, to wait until the line address stable positioning and then send the address, TRCD is an important time parameter of SDRAM, the relevant values refer to the corresponding chip hardware manual. Usually trcd in the number of clock cycles (Tck,clock time), such as the author MINI2440 memory chip is written to TRCD 20nst, if the future memory work in 100MHz, then the RCD must be at least 2 clock cycles, rcd=2.

Figure 2-53 SDRAM read operation sequence diagram

Once the column address has been selected, the specific storage unit has been identified and the rest is waiting for the data to be output through the data I/O channel (DQ) to the memory bus. However, after the column address select the communication number CAS issued, still have a certain amount of time to have data output, from the CAs and read commands issued to the first data output of the time, is defined as CL (CAS latency,cas incubation period). CL is also known as the Read latency (Rl,read Latency) because CL is only present when it is read. CL units, like TRCD, are also the number of clock cycles, depending on the clock frequency (the author's Official Handbook cl=3). However, CAS does not reach the storage unit after the CL cycle. In fact, CAs, like RAS, arrived instantaneously. Because of the chip volume, the capacitance in the storage unit is very small, so the signal must be amplified to ensure its effective identification, this amplification/drive work by S-amp responsible. But it has to have a preparation time to guarantee the signal's transmission intensity, which we call the TAC (Access time from CLK, after the clock is triggered).

1.1.4 SDRAM pre-charge operation

As can be seen from the structure diagram of the storage body, the original logic state of 1 capacitor after the read operation, the discharge will be converted into logic 0. Since SDRAM's addressing is exclusive, after a read and write operation, if another line of the same l-bank is to be addressed, the original operation line is closed and the row/column address is re-sent. When the original operating line is closed, dram in order to keep the data when the current row is closed, to rewrite the information in the storage body, this charge rewrite and shutdown operation Line process is called pre-charge, when sending a pre-charge signal, means to perform the storage charge, and then close the current L-bank operation line. The override action in pre-charge is the same as the refresh operation (described in detail later), except that the pre-charge is not periodic, but only after the read operation.

1.1.5 SDRAM burst operation

Burst (Burst) refers to the same row in the contiguous storage unit data transmission in a continuous manner, continuous transmission of the number of storage units (columns) is the burst length (Burst long, short, BL).

At present, because the memory controller once read/write P-bank bit-wide data, that is, 8 bytes, but in reality less than 8 bytes of data is rarely seen, so generally have to go through multiple cycles of data transmission, the above read/write operation is to address a storage unit at a time, if you want to read/write continuously , we also address the next unit of the current storage unit, that is, to continuously send the column address and the read/write command (the row address is the same, so no more addressing). Although the same read/write latency allows data transfer to be continuous on the I/O side, it consumes a large amount of memory control resources and is inefficient when data is continuously transmitted in order to fail to enter new commands. To this end, the introduction of a burst transmission mechanism, as long as the initial column address and burst length is specified, the memory will automatically be followed by the corresponding length of data storage unit read/write operation and no longer need the controller to provide the column address continuously, so that, in addition to the first data transmission requires a number of cycles (mainly between the delay, Typically TRCD + CL), then each data is only one cycle away.

Summary below:

The basic read operation of SDRAM requires the control line and address line to issue a series of commands to complete. A valid chip command (active) is issued, and the corresponding L-bank address (BA0, BA1 given) and the line address (A0~A12) are locked. After the chip activation command must wait longer than the TRCD (SDRAM RAS to CAS delay indicator) time, the Read command is issued. After the CL (CAS delay value) clock cycles, the readout data appears sequentially on the bus. At the end of the read operation, a pre-charge (precharge) command is issued to the SDRAM to close the activated L-bank. Wait for TRP time (after the Prechareg command, after the TRP time, before you can access the row again), you can start the next read, write operations. SDRAM read operation support burst mode (Burst mode), burst length is 1, 2, 4, 8 optional.

1.1.6 SDRAM write operation

The basic write operation of SDRAM also requires the control line and address line to issue a series of commands to complete. A valid Chip command is issued, and the corresponding L-bank address (BA0, BA1 given) and the line address (A0~A12) are locked. After a valid chip command has to wait for more than TRCD time, the write command data is sent, and the data to be written is sent to DQ (data line) sequentially. Delay TWR time after the last data is written. Issue a pre-charge command to close the activated page. After you wait for TRP time, you can expand the next operation. Write operations can have both burst and non-burst write two kinds. Burst length same as read operation.

Figure 2-54 SDRAM write operation sequence diagram

1.1.7 SDRAM Refresh

SDRAM is the most important operation of SDRAM because it is constantly refreshing (refresh) to keep the data.

The refresh operation, like the one rewritten in the pre-charge, is read-and-write first with S-amp. But why is there a pre-charge operation to be refreshed? Because pre-charging is a work-line operation on one or all of the  l-bank and is irregular, the refresh has a fixed period, which in turn operates on all rows to preserve data in the memory that has not undergone rewriting for a long time. However, unlike all l-bank pre-charging, the rows here refer to the same rows in all L-bank, while the address of each l-bank in the pre-charge is not necessarily the same. So how often do you repeat a refresh? It is now accepted that the maximum data retention period for a capacitor in a storage body is 64ms (milliseconds, 1/1000 seconds), which means that the cycle time for each row refresh is 64ms. So the refresh interval is:  64m/number of rows S. When we look at the memory specifications, we often see the 4096 refresh Cycles/64ms or 8192 refresh cycles/64ms, where 4096 and 8192 represent the number of rows per L-bank in the chip. The refresh command is valid for one row at a time, and the refresh interval varies with the total number of rows, with 4096 rows of  15.625μs (microseconds, 1/1000 milliseconds) and 8192 rows as  7.8125μs. The refresh operation is divided into two types: Auto refresh, AR and self Refresh, abbreviated as SR. Regardless of the Refresh method, you do not need to provide the row address information externally, because this is an internal automatic operation. For  ar,sdram, there is a line address generator (also called a refresh counter) that is used to automatically generate the row address sequentially. Because the refresh is for all the storage in a row, no column addressing is required, or CAS is valid before  ras. Therefore, AR is also known as CBR (CAS before RAS, column ahead of row positioning) type refresh. Since the refresh involves all L-bank, all  l-bank are stopped during the refresh process, and each refresh takes up to 9 clock cycles (PC133 standard) before it can enter a normal working state, that is, during these 9 clock periods, All work orders can only wait and not execute. After 64ms, the same row is refreshed again, so the cycle is refreshed. Obviously, the refresh operation will certainly have an impact on the performance of SDRAM, but this is not the way, but also the cost of the DRAM relative to the  sram (static memory, no need to refresh the data can still be retained) costs. The SR is mainly used for data preservation in the sleep mode low power state, the most famous application is  str (Suspend to RAM, hibernation hangs in memory). When the AR command is issued, the CKE is placed in an invalid state, and it enters the SR mode, where it is no longer dependent on the system clock, but is refreshed based on the internal clock. All external signals except CKE during the SR are not valid (no external refresh instructions required), and only re-enable the Cke to exit from refresh mode and enter normal operation state.

SDRAM related registers:

(1) Bwscon Register (BUS WIDTH & WAIT CONTROL Register)

Table 2-17 SDRAM Control Register (BWSCON)

Set the bit width and wait status of each bank welding chip according to the memory configuration and chip model of the Development Board

Bwscon, each of the 4 digits corresponds to a bank, and these 4 bits respectively indicate:

L STX: The Data Mask pin (UB/LB) of the SDRAM is started/forbidden, SDRAM does not have high and low bit mask pin, this bit is 0,sram connected with ub/lb pin, set to 1

L Note: The UB/LB data mask pin is used to control the chip read/write high-byte and low-byte (compare hardware manual SDRAM and SRAM wiring diagram)

L WSX: Whether to use the wait signal for memory, usually set to 0

L DWx: Set the width of the welding memory chip, the author Development Board using two pieces of capacity of 32M, 16 bits width of the SDRAM composed of 64m,32 bit memory, so dw7,dw6 bit set to 0B10, the other bank does not have to set the default value.

L BANK0 corresponds to the system boot Bank, this 4 bit is very special, its settings are determined by the hardware jumper, so do not set

L Bwscon Set Result: 0x22000000

(2) bankcon0~bankcon5 (BANK CONTROL REGISTER)

Table 2-18 bankcon0~bankcon5 Control Register (BANKCON0~BANKCON5)

These 6 registers are used to set the access timing for the corresponding BANK0~BANK5, with the default value of 0x700

(3) bankcon6~bankcon7 (BANK CONTROL REGISTER)

Table 2-19 bankcon6~bankcon7 Control Register (bankcon6~bankcon7)

Since the memory is soldered to the two banks, the memory driver is primarily set up for these two registers

L MT: Set the Bank6~bank7 memory type,

00=rom or SRAM 01 = reserved

10= reserved 11=sdram

Memory is SDRAM, set to 0B11, corresponding should be set TRCD and scan bit, other bits and SDRAM independent

L Trcd:ras to CAS delay line address selection to the address of the optional delay, this parameter to see the memory of the extension of the operating principle of the explanation, the author memory chip for the hy57v561620, by its chip manual know its TRCD for a minimum of 20ns, if the memory work in 100MHz, This value must be at least 2 clock cycles, typically set to 3 clock cycles, so set to 0B01

L Scan:sdram Column Address number SDRAM, the author memory chip is hy57v561620, column address number is 9, set to 0B01

L BANK6,BANK7 Setting result is: 0x18005

(4) Refresh (refresh CONTROL REGISTER)

Table 2-20 Refresh frequency Settings Register

SDRAM refresh valid, refresh frequency setting register (refresh)

L Refen: Turn on/off refresh function, set to 1, turn on refresh

L Trefmd:sdram Refresh mode, 0=cbr/autorefresh, 1=self refresh, set to 0, auto refresh

L TRP: Line address to select the pre-charging time, generally set to 0B00 can be

L TSRC: Single-row refresh time, set to 0B11.

L Refresh Counter: Number of memory storage unit refreshes, calculated using the following formula:

Refresh Counter = 2^11 + 1–sdram clock frequency (MHz) * SDRAM refresh period (US)

SDRAM refresh period, that is, memory storage unit interval needs to be refreshed, the front memory working principle analysis that the capacitance data storage limit is 64ms, I use memory chip each L-bank total of 8192 lines, so each refresh maximum interval is: 64ms/8192 = 7.8125uS, if the memory is operating at external crystal frequency 12MHz, refresh Counter = 1955, if the memory is working in 100MHz, then refresh Counter = 1269 (Take large integer)

L The Refresh register is set to:

0x8e0000 + 1269 = 0x008e04f5 (HCLK = 100MHz)

0x8e0000 + 1955 = 0x008e07a3 (hclk = 12MHz)

(5) Banksize Register (banksize Register)

Table 2-21 banksize Registers (banksize)

Set the burst mode of memory, power saving mode and memory capacity.

L burst_en: Open burst mode, 0 = arm core Prohibit burst 1 = open burst, set to 1, turn on burst

L Scke_en: Whether to use SCKE signal as power-saving mode control signal, 0 = Do not use SCKE signal as power-saving mode control signal 1 = Use SCKE signal as power-saving mode control signal, usually set to 1

L Sclk_en: Set input operating frequency to memory, 0 = input SCLK frequency continuously, even if no memory operation is entered, 1 = SCLK frequency is entered only when memory data operation, usually set to 1

L Bk76map: Set BANK6/7 memory capacity, the author uses the Development Board memory for two 32M memory chips in parallel to 64M, they are all external to Bank6, so select 0b001

L Banksize Register set to: 0XB1

(6) SDRAM mode setting register MRSRX (SDRAM mode register set Register)

Table 2-22 SDRAM Mode Setup register (MRSRX)

This register is used to set the CAS latent period, can be manually set only Cl[6:4] bit, through the previous memory working principle, I use the Development Board cl=3, that is 0b011

L MRSR6,MRSR7 set to: 0x00000030

Analysis of Linux memory layout based on mini2440