Analysis of open-circuit mechanism in the x86_64 APIC of Linux

The working principle of the interrupt controller between different CPU systems is quite different, this article is the sister of "the analysis of circuit breaker in Linux MIPS64R2 PCI", mainly analyzes the principle, interrupt configuration and processing process of broadwell-de x86_64 APIC. And try to answer the following questions:

• Why is the x86 used in the IO-APIC/LAPIC framework, and what is the value of it?
• Pin/irq/vector difference, function, value range and distribution mechanism?

x86_64 APIC Key Concepts Pin

The pin here refers specifically to the APIC's interrupt input pin, which is connected to the interrupt input signal of the internal and external devices. As you can see, the maximum pin value is limited by the number of APIC pins, and the current value range is [0,23]. of which [0, 15] These 16 pin, based on the reasons of compatibility with the PIC, for a fixed purpose; pirq[a. H] These 8 pins are PCI IRQ pins, which provide interrupt routing for PCI devices, where pirq[a. D] for the pure interrupt pin,pirq[e. H] can be configured as an interrupt pin or GPIO pin.

Which pirq the internal device is broken from, which can be set by the Dxxir (device XX Interrupt Route Register) register, and which APIC PIN the external device uses, which is fixed when the hardware PCB is designed.

Why does the device interrupt go through the APIC and connect to the CPU instead of directly to the CPU? There are two reasons: 1 There is a large number of external devices, but the CPU interrupt pin and other resources are very limited, can not meet all the direct connect demand; 2) If the device is disconnected from the CPU, the connection relationship is fixed with the hardware, so the requirements of the MP system, such as interrupt load balancing, cannot be realized.

Vector

Vector is the concept of CPU, in terms of CPU cores, it is interrupted by the vector logo, see the following section of the circuit breaker introduced by the principle.

vector is the IDT table ( idt_table ) is indexed.

0 0 }},};

The number of vectors is determined by the hardware, and thebroadwell-de x86_64 supports up to 256 vectors. The first 32 are reserved for the system and others are dynamically allocated by the operating system.

vector provides support for priority and affinity binding, Vector High 4 bits are priority, 0 lowest, 15 highest. The CPU only handles vector interrupts with a priority higher than lapic TPR value.

Why do you add a vector concept beyond the IRQ, and can the two be merged? No, the main reason is that the vector is for each CPU core, describing each CPU to check escalation interrupt priority processing and affinity relationship, and IRQ is global, it maintains all CPU cores on the interrupt processing related information.

Irq

In the PIC and single-core era, the IRQ, vector, pin concept is really three, IRQ is the PIC controller pin PIN, IRQ also implies interrupt priority, for example, IRQ0 than IRQ3 has a higher priority. When entering the MP multi-core era, the multi-core CPU interrupt processing brings many problems (such as how to decide which interrupt is processed at which core, how to ensure the load balance on each core), in order to solve these problems, vectors, pins and other concepts are stripped from the IRQ, the IRQ only represents The total number of interrupts supported by all CPU cores, as Irq_desc's index maintains information about interrupt handling.

The total number of IRQ is calculated in the following way, Nr_irqs is the total number of interrupts supported by all CPU cores, Nr_irqs is the initial value of Nr_irqs.

When the IRQ is large, statically allocating the Irq_desc table is not a sensible decision, and the kernel uses radix tree to organize the Irq_desc, which is Irq_desc_tree

Nr_irqs_gsi = -Nr_cpu_ids= -X= The number of IRQ sources we can talk about = nr_irqs_gsi+8*nr_cpu_ids+nr_irqs_gsi* -=1216Y= The number of IRQs we can possibly Service = Nr_vectors*nr_cpu_ids =4096Nr_irqs= Min (X, Y) = min (1216,4096) =1216nr_vectors= theNr_cpus= -Cpu_vector_limit= -* Nr_cpus = the* Nr_cpu_ids =4096Max_io_apics= -Io_apic_vector_limit= +* Max_io_apics =4096Nr_irqs= Nr_vectors + MAX (cpu_vector_limit,io_apic_vector_limit) =4352

x86_64 The principle of the circuit breaker in PCI equipment

As shown, the local APIC accepts interrupts through the I/O APIC, whichis responsible for processing interrupts into interrupt messages and forwarding them to the local APIC according to certain rules.

as shown, the local APIC provides the interrupt Request Register (IRR) and in-service re Gister (ISR) 2 registers, while processing a vector, caches an identical vector,vector through 2 256-bit registers, 256 bit represents 256 possible vectors, 1 indicates that the corresponding vector request is being processed or being processed.

The local APIC handles interrupts as a vector value in order of precedence. Each vector is 8-bit, high 4 bits as interrupt priority, 1 lowest, 15 highest. Vector 0-31 is reserved for the Intel and IA-32 system, so the available interrupt priority is 2-15.

In addition, the local APIC provides task-priority register (TPR), processor-priority Register (PPR) to set the local APIC's task priority and CPU priority, but I/O This interrupt cannot interrupt a task running on the current CPU core when the interrupt vector priority of the APIC forwarding is less than the setting of the local APIC TPR, and this CPU core does not handle this interrupt when the interrupt vector priority is less than the setting of the local APIC PPR. By dynamically setting up TPR and PPR, the operating system can realize the real-time demand of the operating system and interrupt load balancing requirements.

Interrupt Handling Process

The interrupt handling process of the Broadwell-de x86_64 is similar to that in Linux MIPS64R2 PCI in the mechanism analysis, where x86_64 gets the interrupt vectors to be processed from the AX register instead of the specific registers of the APIC. Then, from the VECTOR_IRQ array, the vector is queried for the IRQ number to which it is based.

Unsignedint__irq_entry DO_IRQ (structPt_regs *regs) {    structPt_regs *old_regs =Set_irq_regs (regs); /*High bit used in ret_from_ code*/unsigned vector= ~regs->Orig_ax;    unsigned IRQ;    Irq_enter ();    Exit_idle (); IRQ=__this_cpu_read (Vector_irq[vector]); if(!Handle_irq (IRQ, regs))        {ACK_APIC_IRQ (); if(Printk_ratelimit ()) Pr_emerg ("%s:%d.%d No IRQ handler for vector (IRQ%d) \ n", __func__, smp_processor_id (), vector, IRQ);    } irq_exit ();    Set_irq_regs (Old_regs); return 1;}

Interrupt Configuration Process

1. Dynamically assign IRQ to Irq_bitmap_bits (Nr_irqs + 8196) BITMAP data structure management;
2. Dynamically allocating vectors, in order to ensure maximum utilization of vector priority on local APIC, reduce interrupts with the same vector priority, and allocate vectors in 16 intervals;
3. Configure the vector and IRQ mapping table: VECTOR_IRQ table;
4. Initialize the Irq_desc;
5. Configure APIC Pirq[a. H] pin PIN properties;
6. Configure the I/O APIC pin with vector mapping table: REDIR_TBL Register, total 24 redir_tbl entries, corresponding to 24 pin pins. In addition to defining the appropriate vectors, it is also supported to define interrupt pins with the following functions: Define this pin interrupt escalation to the specified local APIC or local APIC group via the I/O APIC, interrupt trigger mode, interrupt mask, etc. See the table below.

--eof--

Analysis of open-circuit mechanism in the x86_64 APIC of Linux