Analysis on the pae__linux of Linux kernel memory management

Analysis on Linux PAE of kernel memory management

The early Intel processors used 32-bit physical addresses from 80386 to Pentium, which theoretically allowed access to 4GB of RAM. However, large servers require more than 4GB of RAM to run thousands of processes at the same time, and in recent years this has been stressful for Intel, so it must extend the RAM capacity supported by 32-bit 80x86.

Intel has met these requirements by increasing the number of pins from 32 to 36 on its processors, and can address 64GB. At the same time, a new paging mechanism (physical address Extension) is introduced to convert 32-bit linear address to 36-bit physical address to use the added physical memory, and to open the PAE support by setting the 5th bit of CR4. The PAE is introduced to access more than 4GB of RAM, the linear address is still 32 bits, and the physical address is 36 bits.

64GB of RAM is divided into 2^24 page boxes, and the Physical Address field of the page table entry is expanded from 20 to 24 bits. The PAE table entry must contain 12 flag bits and 24 physical address bits, the sum of which is 36, and the page table entry size changes from 32 bits to 64 bits. So the original page box has 1024 entry, now has 512 entry. The PAE-enabled 80x86 32 uses a Level three page table, the first level being the newly introduced PDPT (page catalog pointer table, which is equivalent to PGD), the second is PMD, and the third is the Pte. PDPT has only 4 entry, each corresponding to 1GB RAM, each entry is 64 bits. The CR3 has 27 bits as the starting address for the PDPT.

CR3 uses 20来 to store the starting address of the page directory before the PAE is turned on, and 27 bits are used to store the starting address of page directory pointer table after the PAE is turned on.

The bottom is divided into two situations to discuss, one is ps=0, the other is Ps=1:

when the 5th bit of the CR4 is set (PAE is turned on), the 4th bit is placed (open PSE)

Linear address 31~30, used to point to a PDPT entry linear address 29~21, used to point to a PMD entry linear address 20~0 for offset in 4MB large pages

when the 5th bit of the CR4 is set (PAE is turned on), the 4th bit is cleared (off PSE)

Linear address 31~30, used to point to a PDPT entry linear address 29~21, used to point to a PMD entry linear address 20~12, which points to a PTE linear address 11~0 for offset in 4KB pages

how to access 64GB.

You can see the 2^2*2^9*2^9*2^11=4GB from the top level three pagination and still access the 4GB. Visit the 64GB method as follows:

Modify the value in CR3 to point to a different pdpt, which points to a different 4GB modified PDP entry to point to a different PMD table, which points to different 1GB
But in fact there is no access to such large memory, the actual available memory is limited to 16GB, because if there is 64GB, then each struct page structure requires 32 bytes, a total of 512MB, so that the Zone_normal kernel address space is heavily occupied, this is not allowed.