ARM Instruction Set

Features:
Load/Store Structure (memory operations only include load and store, and all other operations are completed in registers)
32-Bit fixed instruction width
3. Address Instruction format (both source operands and result registers are specified independently)
Each Command is executed in a condition.
A normal operation and a normal ALU operation can be completed simultaneously in a single instruction executed in a single cycle.

Automatic address change

Register Model
In User Mode
15 32-bit universal register heap for R1-R15, R15 for PC register
CPSR Status Register four-digit (N), Z (0), C (carry), V (overflow) Flag

Classification:
+ ------------- + ----------- +
| Data Processing Instruction | data transmission instruction | control flow instruction |
+ ------------- + ----------- +

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Data processing commands: perform arithmetic or logical operations on data in registers
Simple register operation
Arithmetic Operation: ADD, ADC, SUB, SBC, RSB, RSC
Note: RSB and RSC are inverse subtraction and Inner Inverse subtraction, respectively.
Example: ADD r0, r1, r2; r0 = r1 + r2
RSB r0, r1, r2; r0 = r2-r1
Logical operations by bit: AND, ORR, EOR, BIC
Note: bitwise and, bitwise OR, bitwise OR, and not
Example: BIC r0, r1, r2; r0 = r1 and not r2
Register transfer operation: MOV, MVN
Note: MVN is a bitwise reverse transfer.
Example: MVN r0, r2; r0 = not r2
Comparison: CMP, CEN, TST, TEQ
Note: comparison, reverse comparison, bit test, and test are equal
Example: TEQ r1, r2;
Note: The sequential format of operands is the result register, the first and second operands.
Immediate count operation:
Note: Add # to the front of the number to indicate the immediate number, and add # & to indicate the hexadecimal instant number.
Example: ADD r3, r3, #1; r3 = r3 + 1
AND r8, r7, # & ff; r8 = r7 & 0xFF
Register shift operation: Four address commands
Shift command: LSL, LSR, ASL, ASR, ROR, RRX
Description: Logical shift left, logical shift right, arithmetic shift left, arithmetic shift right, cyclic shift right, and extension
One-digit cycle shifts right
Example: ADD r3, r2, r1, LSL #3; r3 = r2 + (r1 <3)
Set the condition code:
Note: you can set a condition code (NZCV) for any data processing commands. You can only set a condition code for comparison operations.
Set the condition code. If you want to set the condition code for other data processing operations, you need to add S
Operation code.
Arithmetic Operations (including CMP and CEN) are used to set all flags Based on arithmetic operation results.
Bit, logical and transfer operations do not produce meaningful C or V values.
If N and Z are set, V is retained. If no shift operation is performed, C is retained.
To C.
Example: ADDS r2, r2, r0
ADC r3, r3, r1
Multiplication operation:
Note: The second operand cannot be an immediate number.
The result register cannot be the source register.
If the bit S is set, the flag V is retained, and the flag C is no longer meaningful.
For long multiplication, the 32-bit high valid bit is placed in the second result register.
Example: MUL r4, r3, r3; r4 = r3 * r2
MLA r4, r3, r2, r1; r4 = r3 * r2 + r1

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Data transfer command: transfers data between ARM registers and memory
Basic Data Transmission commands
Load/Store commands for a single register
Multi-register Load/Store commands
Single Register switch command: It is mainly used in system-level programs to implement atomic operations.
Addressing Mode: ARM's data transmission Commands include indirect addressing of registers, base offset, and base address change,
Note: In any situation, an ARM register is required to store the address, which is close
The address of the data to be transferred.
Example: LDR r0, [r1]; the content of the memory location represented by the value in r1 is read into r0
STR r0, [r1]; write r0 to the memory location represented by a numerical value in r1

Pre-indexed)
Note: The base address register does not contain a definite address. The base address cannot exceed 4 kb.
Offset to address
Example: LDR r0, [r1, #4]; Addressing r1 + 4
The front address of the automatic address change:
Note: When the address is changed automatically, the base address register is modified at the same time.
Example: LDR r0, [r1, #4]! Address r1 + 4 and set r1 + = 4
Post-address change (post-indexed)
Note: No offset addressing is added to the base address. The offset is used only as the base address correction.
Example: LDR r0, [r1], #4; Addressing r1, and adding r1 + = 4
Arbitrary byte alignment command: LDRB

Multi-register data transfer and block transfer (block transfer omitted)
Note: several registers are simultaneously accessed, and a single entry is allowed for any sub-sets of 16 registers.
Command Transmission. Supports automatic address change
Example: LDMIA r1, {r0, r2, r5}; Replace [r1], [r1 + 4], [r1 + 8]
Read r0, r2, r5

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Control Flow commands
Transfer Instruction (branch)