Arm-linux Memory Management Learning Notes (1)-The hardware principle of the memory page table __linux

Linux kernel focuses on the programming wisdom of the world's top programmers, and remembers the four main functions of the operating system: The process scheduling memory management device-driven network. Engaged in the embedded software development work, to the equipment drive and the network contact more. and the process scheduling and memory management contact less, more is at a respectful distance.
I understand that in the kernel development has a deeper level of technical progress, should be the kernel of memory management process scheduling and other deep technology has a certain understanding. However, these 2 pieces of content is the core of the kernel part of the actual kernel development work involving less, there are few problems to enter into the study, there is no systematic information on the Internet to explain, learning is not easy.
In the spirit of my not in hell, who into the principle of hell, this period of time to use the work of the memory management of some research, combined with the work of some memory management problems, the memory management framework has a little understanding. Can only say that this point of understanding makes me more awe of the kernel, do not say process scheduling, memory management alone enough to write a 500-page book.
My understanding of memory management can be divided into page table mechanism and memory allocation mechanism of two large chunks, this time the study also just let me on the page table mechanism some understanding. First write a few articles to write the page table mechanism, the page table mechanism details, and then to learn memory allocation mechanisms, such as BOOTMEM and slab partner system.
Process scheduling is a bigger hole than memory management, and if you're lucky enough to crawl out of the big hole in memory management, jump to the pit of process scheduling.
Suddenly feel the burden on their shoulders is very heavy, this may be the role of the blog, to share their knowledge to everyone, but also let everyone urge themselves to further study.
But they are only a few years to participate in the work of primary school students, trying to analyze these advanced knowledge, there will be mistakes and errors, but since sharing out, is to let everyone and I together quweicunzhen, to improve. So I hope that we can make more suggestions and work together.

Because memory management is a relatively abstract knowledge, it is based on three principles:
(1) with a number of questions to study, to raise some questions, from these points of doubt into
(2) Drawing the abstract knowledge into a logical diagram to make the frame clearer
(3) instantiation, as far as possible by the actual equipment to the memory management research

This series of articles is based on the ARM architecture, Linux kernel version number 3.4.55

The Linux kernel page table mechanism is simply to manage the device real physical address and virtual address of a dynamic or static mapping, is based on hardware MMU, the processor must provide MMU memory management Unit, Linux page table mechanism to work properly, the two complement each other.
Learning Kernel memory Management If it is divorced from the MMU hardware principle, only to learn its software logic, it is really difficult to understand. In the final analysis, the software code logic is for the hardware service, just in order to give full play to the hardware functions, so learning Linux memory management mechanism, first of all to learn the processor under the framework of the MMU working principle, so that we understand the logic of the page table mechanism is very helpful. (as a low-level software engineer, nothing to turn over datasheet very useful ah, more from the hardware thinking to consider the problem)
MMU is the hardware logic inside the processor core, so only in the processor core datasheet in detail, arm MMU logic for different versions of the processor, I have a arm920t manual, read the MMU chapter, I have the following several questions to solve:

a MMU utilizes a TLB to convert between PA (physical address) and VA (virtual address), and the processor addressing is addressed directly in the TLB. However, when the kernel initializes, the page table is created in memory, and the page table is related to the TLB.
The MMU of ARM has 64 instruction TLB and data TLB respectively, the virtual address conversion of processor addressing is MMU to match between TLB to complete mapping, but in kernel initialization will build page table Swapper_pg_dir in memory (this process can see another blog post: http ://blog.csdn.net/skyflying2012/article/details/41447843) and configures the address in the CP15 register. What is the relationship between this page table and arm's TLB?
920T MMU Chapter I found the answer, as follows:

When the CPU accesses the VA (virtual address), the TLB hardware completes the conversion of VA to PA (physical address), but if there is no Hardware unit translation table Walk for that VA's TLB Entry,mmu The Hardware (Page Table index unit) Indexes the memory page table provided by the CP15 register C0, makes address translation, and gets the PA for access. and the page table information is updated to the TLB, and the page table is not a concept with TLB, a TLB is a cache hardware for the memory page table.
that is, ARM's MMU not only uses TLB to address translation, but also resolves and addresses the page tables provided in memory, while the TLB stores some of the most commonly used addresses for CPUs. The TLB is fast, which speeds up address translation efficiency.
If the page table information for this VA is not found, MMU emits an exception to the CPU (which emits either data abort or instruct abort, depending on data or instruct), and the page table fills in the exception handler function.
This also gives me an idea of why the kernel-initialized create_mapping function (the key function of the memory map) and the page-fault exception handling function Do_page_fault see updates to the Memory pages table, not the TLB. because arm's MMU itself uses the memory page table.
and arm's direct manipulation TLB is more complex than manipulating the memory page table so that MMU updates the TLB based on the memory page table.
Of course, the memory page table that arm's MMU can manipulate is also in a fixed format, which is our next problem.

Second look at the kernel code, ARM Linux use of Level two page table mapping, then arm's MMU hardware how to complete the conversion of VA to Pa.
ARM's MMU uses the memory page table how to complete the address conversion, the manual diagram will mmu the table of Operations page several ways to list, as follows:

If this picture can fully understand, ARM's MMU hardware address translation even if fully understood. Can see arm MMU complete address conversion way there are a lot of kinds, total divided into 2 kinds, section-mapping and page-mapping. Linux's two-level page table style belongs to page-mapping, but 2 ways to map the Linux kernel are used, this later.
The memory page table that we hand over to the CPU (C0 written to CP15) is a page table (also known as a page catalog) address that has a total of 4,096 indexes, each with 4 bytes, and a single table item can map 1MB of address space. A page table of 16KB size can cover the maximum 4GB space that 32-bit CPUs can address.
It can be imagined that querying these 4,096 indexes requires only a high 12 bits of 32-bit virtual addresses, the CPU first obtains the page directory base address (TTB), plus the high 12 bits of the virtual address to be converted, that is, the page directory entry for the virtual address is obtained. This process is the same for both section-mapping and page-mapping, so how do you distinguish between mapping, the key in the page directory entry with the minimum 2bit, as follows:

MMU according to the page catalog entry minimum 2bit to determine what to do next, all 0, invalid page directory, MMU will send the CPU to issue an exception. Page-mapping will also be subdivided into coarse page table (thick page) and fine page table (fine page tables), whether the two-level page table maps 64k/4k or 1K pages, and the Linux kernel uses 4K pages, So this article focuses on 4K pages in the Rough page table.
Next look at the section-mapping and page-mapping of the actual address conversion principle.

1 section-mapping
A graph flow is as follows:

This diagram clearly illustrates the working principle of the section-mapping mode, according to the high 12-bit index and TTB added to get the page catalog items, MMU found that the lower 2 bit 10, is section-mapping, take the page directory entries of the high 12-bit and virtual address of the lower 20-bit stitching, The physical address is obtained and the conversion is completed.

2 page-mapping
A graph flow is as follows:

This illustrated the Page-mapping way of 4 K page works, is a two-level page table, can be subdivided into 5 steps:
(1) MMU is removed from the TTB (page directory) base address by the C0 of CP15 and is added to the VA (virtual) 12-bit height to obtain the corresponding page catalog entry value for that VA in the page catalog.
(2) MMU get page Catalog entry minimum 2bit, is 01, indicating this map 1MB data is 4k small page page-mapping.
(3) MMU gets the high 22 bits of the page directory entry (the page table is 256x4=1k, so the page table base address is 1K-aligned) is the page-table-basis, which is added to the center 8 digits of VA, which is the corresponding page table entry address for the VA, to get the page table entry value for VA (page entry)
(4) MMU gets the high 20 bits of the page table entry value, which is the corresponding physical address of the 4K page, which is added to the VA low 12 bit (that is, the offset in the 4K page), which is the corresponding physical address of Va.
(5) MMU access to the physical address, the CPU for the read and write operation

The above illustrates the 2 kinds of mapping mode of the actual address conversion logic, you can see that, regardless of section-mapping or page-mapping, in the first page table is complete map of 1MB address, and page-mapping Second Level page table entry to complete the map of 4K pages.
Therefore, regardless of the physical address in the first-level page table entry or the Second Level page table entry, there will also be a lot of bits that are free, and the spare bit completes the access to the mapped address and the control of the operation attributes, mainly including the AP bit (access permission) and the cache attribute bit, For section-mapping, the control bit is in the first page table (because it is only one level), and the First Level page table entry level of section-mapping is defined as follows:

For page-mapping, the control bit is primarily in the second-level page table entry, defined as follows:

For these bit here is not detailed, to be followed by a specific problem in the analysis.

Here, for ARM's MMU in the actual address conversion work principle has been explained clearly, with these hardware basis, and then to learn the Linux Kernel page table mechanism will be more relaxed.
Next, we'll dive into the code of Linux to analyze it.