Assembly write startup code shut watchdog and set stack and call C language and Icache__c language

Refer to Teacher Zhu Tutorial video explanation, video link address: http://edu.51cto.com/lecturer/user_id-9584512.html

1. Guard Dog

Watchdog (Watch dog timer watchdog timers)
Physically, the watchdog is actually a timer (similar to a real-life alarm clock), and hardware is an internal peripheral inside the SOC.
Wtcon (0xe2700000), where BIT5 is a watchdog switch: 0 delegates off, 1 for open
Why do you have to shut the guard dog?
General CPU design, the watchdog defaults to work after the CPU starts, and the advantage is that there is no gap or loophole, and the downside is that when the boot code segment is not convenient for us to feed the dog (or to feed the dog), the watchdog will be reset, so in order to be lazy we start off the watchdog at the front Then, after the system starts up, decide whether to turn on the watchdog (once it is turned on, you must also provide the dog).
In the Irom code (BL0) inside the s5pv210, the watchdog has actually been shut down. So our startup code is actually no need to shut down also nothing, that is, today's write shut down the watchdog code after running no phenomenon (no phenomenon is normal phenomenon).
A lot of CPU inside is not BL0, therefore also no one to you to shut the watchdog, must write the code in front of the boot code to shut the watchdog dog. 2, c voice run-time needs and the significance of the stack

The "C Voice Runtime (runtime)" requires certain conditions, which are provided by the Assembly. C Speech Runtime is mainly the need for stacks.
C speech and the relationship between the stack: C voice of the local variables are used to implement the stack. If our Assembly section does not provide a reasonable and reasonable stack address for the C section, then the local variables defined in the C code will come down empty and the entire program would run.
The commonly used SCM program or application does not go to set the stack, c program can also run. The reason is that when there is hardware initialization in the SCM, a default available stack is provided. The C program written in the application is not all program code, the compiler (GCC) in the link will help us automatically add a head, this head is a guide to our C program can execute a section of the compilation of Code, This code helps our C program to set up stacks and other run-time needs. 3, CPU mode and the stack in various modes

In arm 37 registers, each mode has its own SP register (R13), why has this design.
If all modes are using the same SP, it means that the entire program (the kernel of the operating system, the user-written application) is a stack. Once your application goes awry (such as a stack overflow), the operating system stack is corrupted, causing the entire program to crash. Such an operating system design is very fragile and unreasonable.
The solution is to use different stacks in each mode. independent of each other.

The system enters SVC mode by default after reset
How do we access the SP in SVC mode? Very simple, first set the mode to SVC, and then directly operate the SP.

The stack must be the current segment of available memory (which means that the place must have an initialized, accessible memory, and that the memory command is used as a stack and will not be occupied by other programs)
The current CPU has just been reset or just started, the external DRAM has not been initialized, the current available memory is only internal SRAM (because it does not need to initialize to use). So we can only find a section of memory in SRAM as the stack of SVC.
The stack has four kinds: full reduction stack, Mas, empty stack, empty increase stack,
In arm, atpcs (arm about how the program should be implemented a specification) requires the use of a full stack, so no accident is to use full stack. Combined with the memory map in "Irom_application_note", we know that the SVC stack should be set to 0XD0037D80

4. Assembler and C program call each other

Create a new and add a C source file (LED.C) in your project, and note that you want to modify the makefile when you add it
To modify the compilation options in makefile: Arm-linux-gcc-o $@ $<-c-nostdlib
Compile an error (in fact, the connection phase error): Undefined reference to ' __AEABI_UNWIND_CPP_PR1 '
Workaround: Add-nostdlib at compile time to resolve this compilation option. NoStdLib is not using standard function libraries. The standard function library is the compiler's own function library, with-NOSTDLIB allows the compiler linker to select the function library that I write in my program.
After you set up the stack in the assembly startup code, use the method (bl cfunction) to invoke the function cfunction in C language, such as the main function in the MCU (BL main). 5, the use of C language to access registers of the way

The address of the register is similar to the memory address (IO and memory), so the problem here is to read and write in C language registers, that is, the C language to read and write memory address. Follow these steps:

volatile  unsigned int *p = (unsigned int *) 0xe0200240;
*p = 0x11111111;

The above two sentences can actually be simplified as follows:
* ((volatile unsigned int *) 0xe0200240) = 0x11111111;
Can operate in this way, direct operation Rgpj0con and Rgpj0dat can manipulate J0 io feet

#define GPJ0CON     0xe0200240
#define GPJ0DAT     0xe0200244

#define RGPJ0CON    * (volatile unsigned int *) (Gpj0con)
#define RGPJ0DAT    * (volatile unsigned int *) gpj0dat)

6, the magical volatile

The role of volatile is to let the program compile, the compiler does not optimize the program. Optimization is sometimes OK, but there are times when it is wrong to be smart. If one of your variables is variable and you don't want the compiler to help us with optimizations, add volatile to the variable definition.
Add no difference, depending on the compiler. If the compiler does optimize, there is a difference; if the compiler itself does not optimize, there is no difference.
In our case (compiler is ARM-2009Q3), the actual test plus no effect is the same.

void delay (void)
{
    //volatile let the compiler not optimize, so as to really reduce, can consume time, realize delay
    volatile unsigned int i = 900000;   
    while (i--);                            
}

7, Icache

What is Icache. What's the use.
Cache is a kind of memory called high speed memory.
From Capacity: CPU < Register < cache < DDR
From speed: CPU > Register > Cache > DDR
Cache exists because the speed difference between registers and DDR is too large, the speed of DDR can not meet the needs of the Register, that is, also can not meet the needs of the CPU, no cache will pull down the speed of the entire system.
The CPU supply chain of the whole system is: Register +cache+ddr+ hard Disk/flash Four order composition, this is the result of compromise after considering performance and cost synthetically.
The s5pv210 has 32KB Icache and 32KB dcache cache and 512KB level two cache.
Icache is used to cache instructions, Dcache are used to cache data.

Cache meaning: The instructions are usually placed in the hard disk/flash, the runtime read to the DDR, and then read from the DDR register, and then sent to the CPU by the register. However, the speed of the DDR and register is too large, if the CPU runs a sentence and then go to the DDR read the next sentence, then the CPU speed is completely DDR to slow down, the solution is to use Icache.
Icache work, will be the CPU is running instructions to read the next few sentences in advance to the Icache (CPU design has a basic principle: Code execution, the next sentence to execute the current code next to the possibility of a large number of code). The next CPU to instructions, cache first check their prepared cache instructions there is no CPU required this command, if there is a direct to the CPU, if not the need to read from the DDR to the CPU, and at the same time do a series of actions: Clear cache, cache. 8, Irom in the BL0 to the cache operation

First of all, all the movements of Icache are automatic, without human intervention. All we have to do is turn on/off the Icache.
Second, in the 210 Irom, BL0 has opened the Icache. So the phenomenon that I saw before is the phenomenon that icache open.
Assembly code Read-write CP15 to switch Icache

MRC P15, 0, R0, C1, C0, 0;                 Read out CP15 C1 to r0 in
Bic r0, R0, # (1<<12)                       //bit12 Place 0 off Icache Orr r0,
r0, # (1<<12)                  //bit12 1 Open Icache
MRC p15, 0, R0, C1, C0, 0;